Advertisement
Quick Links
a
Silicon Anomaly List
ABOUT ADSP-CM411F/412F/413F/416F/417F/418F/419F SILICON ANOMALIES
These anomalies represent the currently known differences between revisions of the ADSP-CM411F/412F/413F/416F/417F/418F/419F
product(s) and the functionality specified in the ADSP-CM411F/412F/413F/416F/417F/418F/419F data sheet(s) and the Hardware
Reference book(s).
PRODUCT REVISIONS
A product revision letter with the form "-x" is branded on all parts. The implementation field bits <31:28> of the JTAG0_IDCODE register
for the processor and <15:0> of the STATUSREG0 register for the Analog Front End (AFE) can be used to differentiate the revisions as
shown below.
Product REVISION
JTAG0_IDCODE<31:28>
C
0x2
0.0
0x1
ANOMALY LIST REVISION HISTORY
The following revision history lists the anomaly list revisions and major changes for each anomaly list revision.
Date
Anomaly List Revision
07/24/2017
C
06/27/2016
B
12/17/2015
A
NR004483C
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
with ARM Cortex-M4/M0 and 16-Bit ADCs
ADSP-CM411F/412F/413F/416F/417F/418F/419F
AFE_STATUSREG0<15:0>
0x3082
0x3080
Data Sheet Revision
Additions and Changes
PrB
Added Silicon Revision C
Added Anomalies: 17000067, 17000080, 17000082,
PrB
Added Anomalies: 17000063, 17000064, 17000066, 17000075,
17000076,
Revised Anomalies: 17000040, 17000041, 17000042, 17000043,
17000046, 17000049,
PrA
Initial Version
Document Feedback
Mixed-Signal Control Processor
17000077
17000059
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Technical Support
17000083
©2017 Analog Devices, Inc. All rights reserved.
www.analog.com
Advertisement
Related Manuals for Analog Devices ADSP-CM411F
Summary of Contents for Analog Devices ADSP-CM411F
- Page 1 ADSP-CM411F/412F/413F/416F/417F/418F/419F ABOUT ADSP-CM411F/412F/413F/416F/417F/418F/419F SILICON ANOMALIES These anomalies represent the currently known differences between revisions of the ADSP-CM411F/412F/413F/416F/417F/418F/419F product(s) and the functionality specified in the ADSP-CM411F/412F/413F/416F/417F/418F/419F data sheet(s) and the Hardware Reference book(s). PRODUCT REVISIONS A product revision letter with the form "-x" is branded on all parts. The implementation field bits <31:28> of the JTAG0_IDCODE register for the processor and <15:0>...
- Page 2 ADSP-CM411F/412F/413F/416F/417F/418F/419F Silicon Anomaly List SUMMARY OF SILICON ANOMALIES The following table provides a summary of ADSP-CM411F/412F/413F/416F/417F/418F/419F anomalies and the applicable product revision(s) for each anomaly. Description 17000033 SMC Byte Enable Signals Tri-State during Read Operations 17000035 Timer0 Status Interrupt Is Not Functional...
- Page 3 Silicon Anomaly List ADSP-CM411F/412F/413F/416F/417F/418F/419F DETAILED LIST OF SILICON ANOMALIES The following list details all known silicon anomalies for the ADSP-CM411F/412F/413F/416F/417F/418F/419F including a description, workaround, and identification of applicable product revisions. 17000033 - SMC Byte Enable Signals Tri-State during Read Operations: DESCRIPTION: During SMC read operations, the byte enable signals (SMC0_ABE0 and SMC0_ABE1) are tri-stated instead of being driven low.
- Page 4 ADSP-CM411F/412F/413F/416F/417F/418F/419F Silicon Anomaly List 17000038 - M0 DMA Debug Halt Is Not Functional: DESCRIPTION: The M0 system's DMA debug logic that halts the DMA traffic does not function when a cross trigger unit halts. The DMA operations may continue in real-time during debug halt.
- Page 5 Silicon Anomaly List ADSP-CM411F/412F/413F/416F/417F/418F/419F 17000043 - ADC Reference Voltages Do Not Match Specification: DESCRIPTION: The ADC reference voltages (VREF0, VREF1, and VREF2) are not calibrated to the specified 2.5 V. WORKAROUND: Use the actual ADC reference voltage values in ADC calculations, not the specified value.
- Page 6 ADSP-CM411F/412F/413F/416F/417F/418F/419F Silicon Anomaly List 17000048 - Monitor ADC Conversion Time Exceeds Specification: DESCRIPTION: The minimum conversion time of the Monitor ADC (ADC0) is 600 ns (instead of 500 ns as per the specifications). Therefore, the maximum sampling rate of the ADC0 is 1.667 MSPS.
- Page 7 Silicon Anomaly List ADSP-CM411F/412F/413F/416F/417F/418F/419F 17000055 - Flash Security Features Are Not Fully Operational: DESCRIPTION: All the security features and key management processes may be exercised. However, flash memory contents are not fully protected by the security measures even if the part is locked. Security measures are planned to be fully functional in production silicon.
- Page 8 ADSP-CM411F/412F/413F/416F/417F/418F/419F Silicon Anomaly List 17000063 - System Watchpoint Units 3 and 4 Incorrectly Alias Master IDs: DESCRIPTION: SWU3 and SWU4 only monitor the 6 LSBs of the SWU ID instead of 9 bits. As a result, the Master ID of the masters that share the same 6 LSBs, but have different MSBs, are incorrectly aliased.
- Page 9 Silicon Anomaly List ADSP-CM411F/412F/413F/416F/417F/418F/419F 17000064 - Back-to-back Writes to Internal SRAM May Be Lost: DESCRIPTION: When back-to-back writes are performed to the same 32 KB bank of the internal SRAM, the first write may be lost if address bit 14 is different (all other bits are the same) on the second write.
- Page 10 ADSP-CM411F/412F/413F/416F/417F/418F/419F Silicon Anomaly List 3. If DMA requires more than 32 KB for writes, ensure that the writes are linear. This issue does not exist in case of a linear addressed DMA. 4. If Read-only DMA buffer has to be initialized, the code and variables of the function performing the initialization must reside in a separate 32 KB bank.
- Page 11 Silicon Anomaly List ADSP-CM411F/412F/413F/416F/417F/418F/419F 17000067 - ADCC Frame Interrupt Status Register Must Be Cleared Between Frames: DESCRIPTION: When the ADCC_NUMFRAMx register is zero, the ADCC_FISTAT.FINTx bit is set after all the events related to a frame have completed. When the ADCC_NUMFRAMx register is non-zero, the ADCC_FISTAT.LFINTx bit is also set after all the events related to all the frames (ADCC_NUMFRAMx + 1) have completed.
- Page 12 WORKAROUND: None. APPLIES TO REVISION(S): ©2017 Analog Devices, Inc. All rights reserved. Trademarks and w w w . a n a l o g . c o m registered trademarks are the property of their respective owners. NR004483C | Page 12 of 12 | July 2017...