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,1752'8&7,21
Figure 1-0.
Table 1-0.
Listing 1-0.
The ADSP-21065L SHARC is a high-performance, 32-bit digital signal
processor for communications, digital audio, and industrial instrumenta-
tion applications.
Along with a high-performance, 180 MFLOPS core, the ADSP-21065L
has a dual-ported, on-chip SRAM and integrated I/O peripherals sup-
ported by a dedicated I/O processor. With its on-chip instruction cache,
the processor can execute every instruction in a single cycle. The
ADSP-21065L is code-compatible with other members of the SHARC
family.
Four independent buses for dual data, instructions, and I/O, and cross-
bar-switch memory connections implement the ADSP-21065L's Super
Harvard Architecture.
The ADSP-21065L provides these features:
• 32-Bit IEEE floating-point computation units—Multiplier, ALU,
and Shifter—that support 180 MFLOPS or 180, 32-bit fixed-point
MOPS.
• Data Register File.
• Data Address Generators (DAG1, DAG2).
• Program Sequencer with Instruction Cache.
• 544 Kbits of user-configurable, dual-ported SRAM.
• External port for glueless interface to SDRAM and other off-chip
memory and peripherals.
ADSP-21065L SHARC User's Manual
1-1
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Summary of Contents for Analog Devices SHARC ADSP-21065L
- Page 1 ,1752'8&7,21 Figure 1-0. Table 1-0. Listing 1-0. The ADSP-21065L SHARC is a high-performance, 32-bit digital signal processor for communications, digital audio, and industrial instrumenta- tion applications. Along with a high-performance, 180 MFLOPS core, the ADSP-21065L has a dual-ported, on-chip SRAM and integrated I/O peripherals sup- ported by a dedicated I/O processor.
- Page 2 • Host port and multiprocessor interface. • DMA controller to support ten DMA channels. • Serial ports with two receivers and two transmitters that support TDM and I • Two programmable timers and twelve programmable, general-pur- pose I/O ports. • JTAG test access port. Figure 1-1 shows the ADSP-21065L’s Super Harvard Architecture, which consists of a crossbar bus switch connecting the DSP core’s numeric pro-...
- Page 3 ,QWURGXFWLRQ Figure 1-2, a detailed block diagram of the processor, shows its architec- tural features. DSP Core Dual-Ported SRAM JTAG Test & NDEPENDENT Instruction Emulation ORTED LOCKS cache 32x48b External Port PROCESSOR PORT PORT DAG1 DAG2 SDRAM Interface Program ADDR DATA DATA ADDR...
- Page 4 a host processor; and another multiprocessing ADSP-21065L. The exter- nal port performs internal and external bus arbitration and supplies control signals to shared, global memory and I/O devices. The documentation set, ADSP-21065L SHARC User’s Manual and ADSP-21065L SHARC Technical Reference, contain ADSP-21065L archi- tectural information and the processor’s instruction set, which developers need to design and program ADSP-21065L-based systems.
- Page 5 ,QWURGXFWLRQ )HDWXUHVDQG%HQHILWV The ADSP-21065L possesses the five central requirements for DSPs estab- lished in the ADSP-2106x Family of 32-bit floating-point DSPs: • Fast, flexible arithmetic computation units • Unconstrained data flow to and from the computation units • Extended precision and dynamic range in the computation units •...
- Page 6 )HDWXUHVDQG%HQHILWV 40-Bit Extended Precision. The ADSP-21065L handles 32-bit IEEE floating-point format, 32-bit integer and fractional formats (twos-comple- ment and unsigned), and extended-precision, 40-bit IEEE floating-point format. The processor carries extended precision throughout its computa- tion units, limiting intermediate data truncation errors. When working with data on-chip, the processor can transfer the extended-precision, 32-bit mantissa to and from all computation units.
- Page 7 ,QWURGXFWLRQ High Level Languages. The ADSP-21065L’s architecture has several fea- tures that directly support high-level language compilers and operating systems: • General purpose data and address register files. • 32-bit native data types. • Large address space. • Pre- and postmodify addressing. •...
- Page 8 )HDWXUHVDQG%HQHILWV :K\)ORDWLQJ3RLQW'63" A digital signal processor’s data format determines its ability to handle sig- nals of differing precision, dynamic range, and signal-to-noise ratios. However, ease-of-use and time-to-market considerations are often equally important. Precision. The number of bits of precision of A/D converters has contin- ued to increase, and the trend is for both precision and sampling rates to increase.
- Page 9 ,QWURGXFWLRQ $'63/$UFKLWHFWXUH The rest of this chapter summarizes the architectural features of the ADSP-21065L SHARC: • DSP core • Dual-ported memory • External port interface • Host processor interface • I/O Processor • Serial ports • DMA controller • Booting •...
- Page 10 $'63/$UFKLWHFWXUH • Two programmable timers and twelve general-purpose I/Os • Four external hardware interrupts These additional features support and enhance the DSP core’s components: • Context switching • Comprehensive instruction set &RPSXWDWLRQ8QLWV The DSP core contains three independent computation units: •...
- Page 11 ,QWURGXFWLRQ The floating-point operations are single-precision, IEEE-compatible. The 32-bit floating-point format is the standard IEEE format, while the 40-bit IEEE extended-precision format has eight additional LSBs of mantissa for greater accuracy. The computation units perform single-cycle operations—there is no com- putation pipeline.
- Page 12 $'63/$UFKLWHFWXUH The Program Sequencer supplies instruction addresses to program mem- ory. It controls loop iterations and evaluates conditional instructions. Using an internal loop counter and loop stack, the processor executes looped code with zero overhead. To loop or to decrement and test the counter requires no explicit jump instructions.
- Page 13 ,QWURGXFWLRQ ,QVWUXFWLRQ&DFKH The Program Sequencer includes a 32-word instruction cache that enables three-bus operation for fetching an instruction and two data values. The cache is selective—only instructions whose fetches conflict with program memory data accesses are cached. This enables full-speed execution of core looped operations, such as digital filter, multiply-accumulates and FFT butterfly processing.
- Page 14 $'63/$UFKLWHFWXUH On the ADSP-21065L, data memory stores data operands, and program memory stores both instructions and data (filter coefficients, for example). This configuration enables the processor to perform dual data fetches when the instruction cache supplies the instruction. The data memory address comes from one of two sources—an absolute value specified in the instruction code (direct addressing) or the output of a data address generator (indirect addressing).
- Page 15 ,QWURGXFWLRQ ,QWHUUXSWV The ADSP-21065L has four external hardware interrupts: three gen- eral-purpose interrupts IRQ , and a special interrupt for reset. The processor also has internally generated interrupts for the timer, DMA con- troller operations, circular buffer overflow, stack overflows, arithmetic exceptions, multiprocessor vector interrupts, and user-defined software interrupts.
- Page 16 $'63/$UFKLWHFWXUH an algebraic syntax for ease of coding and readability. A comprehensive set of development tools supports program development. 'XDO3RUWHG0HPRU\ The ADSP-21065L contains 544 Kbits of on-chip SRAM, organized into two banks: Bank 0 has 288 Kbits, and Bank 1 has 256 Kbits. Bank 0 is configured with 9 columns of 2Kx16 bits, and Bank 1 is configured with 8 columns of 2Kx16 bits.
- Page 17 ,QWURGXFWLRQ ([WHUQDO3RUW,QWHUIDFH The ADSP-21065L’s external port provides the processor’s interface to off-chip memory and peripherals. The 64M × 32-bit word, off-chip address space is included in the ADSP-21065L’s unified address space. The separate on-chip buses—for PM addresses, PM data, DM addresses, DM data, I/O addresses, and I/O data—are multiplexed at the external port to create an external system bus with a single 24-bit address bus and a single 32-bit data bus.
- Page 18 $'63/$UFKLWHFWXUH Vector interrupt support provides efficient execution of host commands. ,23URFHVVRU The ADSP-21065L’s I/O Processor (IOP) includes two serial ports, each with two transmitters and two receivers, and a DMA controller. 6HULDO3RUWV The ADSP-21065L features two synchronous serial ports that provide an inexpensive interface to a wide variety of digital and mixed-signal periph- eral devices.
- Page 19 ,QWURGXFWLRQ commonly used by audio codecs), and TDM (Time Division Multiplex) multichannel mode. The serial ports can operate with little-endian or big-endian transmission formats, with selectable word lengths of three to thirty-two bits. They offer selectable synchronization and transmit modes and optional µ-law or A-law companding.
- Page 20 $'63/$UFKLWHFWXUH %RRWLQJ Applications can boot the internal memory of the ADSP-21065L at sys- tem powerup from an 8-bit EPROM, a host processor, or external memory. The BMS (Boot Memory Select) and BSEL (EPROM Boot) pins select the boot source. Either 8-, 16-, or a 32-bit host processor can boot the ADSP-21065L.
- Page 21 In addition to the software and hardware development tools available from Analog Devices, third parties provide a wide range of tools support- ing the SHARC processor family. ADSP-21065L SHARC User’s Manual...
- Page 22 6XPPDU\RI)HDWXUHV 6XPPDU\RI)HDWXUHV This section summarizes the functional features and benefits of the ADSP-21065L, the design features that balance its DSP core with its I/O components, and lists additional, related ADI literature. )HDWXUHVDQG%HQHILWV Table 1-1. Summary of ADSP-21065L features and benefits Feature Benefits 32-bit processing...
- Page 23 ,QWURGXFWLRQ Table 1-1. Summary of ADSP-21065L features and benefits (Cont’d) Feature Benefits 16K × 32bit (544 Kbits) • Reduces bottlenecks over accesses of user-configurable of off-chip memory. internal memory • Reduces overall system cost, size, and power consumption. • Provides freedom in allocating data and program memory.
- Page 24 SRAM ADSP-21065L 60 MHz Figure 1-4. Balanced performance between the DSP core and I/O $GGLWLRQDO/LWHUDWXUH The following publications can be ordered from any Analog Devices sales office. ADSP-21000 Family Hardware & Software Development Tools Data Sheet ADSP-21065L SHARC Data Sheet...