UG-1674
OPERATING THE ADPA1105-EVALZ WITH A PULSED GATE VOLTAGE
To implement gate pulsed operation, apply a negative voltage
pulse to the ADPA1105 V
GG1
on the ADPA1105 V
and V
DD1
SETUP
All power supply, ground, and control signals are applied to
the P3 and P4 headers of the ADPA1105-EVALZ. For this
mode of operation, pulse the gate voltage between −4 V (off)
and approximately −2.3 V (on) to set the quiescent current
(I
) to approximately 400 mA. The pulse width and duty cycle
DQ
must be approximately 100 μs and 10%, respectively.
OPERATION
Take the following steps to power-up:
1.
Set VDDx (P3 Pin 4, Pin 6, and Pin 8) to 0 V.
2.
Set VGGx (P4 Pin 6, Pin 8, and Pin 10) to off (V
V
= −4 V).
GG2
3.
Set VDD to 50 V.
4.
Turn on the gate voltage pulse (V
between −4 V and approximately −2.3 V).
5.
Fine tune the pulse high voltage to achieve the desired I
(nominally 400 mA) while maintaining the pulse off
voltage level at −4 V.
6.
Apply the RF input signal.
and V
inputs while the voltage
GG2
pins is held constant.
DD2
=
GG1
and V
pulsing
GG1
GG2
Take the following steps to power-down:
1.
Turn off the RF signal.
2.
Turn off the pulse to V
3.
Set VDD to 0 V.
4.
Increase the pulse to V
DQ
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ADPA1105-EVALZ
and V
(V
GG1
GG2
GG1
and V
to 0 V.
GG1
GG2
User Guide
= V
= −4 V).
GG2
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