Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

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ADSP-TS101 TigerSHARC

Processor

Hardware Reference

Revision 1.1, May 2004

Part Number

82-001996-01

Analog Devices, Inc.

One Technology Way

Norwood, Mass. 02062-9106

Table of Contents

Summary of Contents for Analog Devices ADSP-TS101 TigerSHARC

Page 1 ADSP-TS101 TigerSHARC Processor ® Hardware Reference Revision 1.1, May 2004 Part Number 82-001996-01 Analog Devices, Inc. One Technology Way Norwood, Mass. 02062-9106...
Page 2 Analog Devices, Inc. Printed in the USA. Disclaimer Analog Devices, Inc. reserves the right to change this product without prior notice. Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use;...
Page 3: Table Of Contents
DSP Product Information ............xxiii Product Related Documents ........... xxiv Technical Publications Online or on the Web ......xxiv Printed Manuals ..............xxv VisualDSP++ and Tools Manuals ......... xxv Hardware Manuals ............. xxvi Data Sheets ................ xxvi ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 4 Internal Transfer ............... 1-17 Data Accesses ..............1-17 Quad Data Access ............. 1-17 Scalability and Multiprocessing ..........1-18 External Port ................. 1-19 External Bus and Host Interface ........1-19 External Memory ............1-19 Multiprocessing ............1-20 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 5 Broadcast Write ..............2-8 Merged Distribution ............2-8 Broadcast Distribution ............2-8 Data Alignment Buffer ............2-9 Register Access Features ..............2-9 Register Space ................. 2-9 Compute Block Register Files ..........2-10 Merged Access ..............2-11 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 6 PMASK Register ............... 2-19 Interrupt Vector Table Register Groups ......2-20 Debug Register Groups ............2-21 Performance Monitor Counter – PRFCNT ....... 2-23 Performance Monitor Mask – PRFM ........ 2-23 Watchpoint Control – WP0CTL, WP1CTL and WP2CTL 2-25 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 7 Link Port Transmit DMA Register ......... 2-45 Link Port Receive DMA Register ........2-45 DMA Control and Status Register ......... 2-46 Link Registers ..............2-47 Link Port Control and Status Register ......2-47 Link Port Receive and Transmit Buffers ......2-48 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 8 Timer 0 Output Pin .............. 3-10 INTERRUPTS Interrupt I/O Pins ................ 4-2 Interrupt Vector Table ..............4-2 Interrupt Types ................4-3 Level or Edge Interrupts ............4-3 Interrupts Generated by On-Chip Modules ........4-4 Timers ..................4-4 viii ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 9 Exceptions .................. 4-23 CLUSTER BUS External Bus Features ..............5-2 Bus Interface I/O Pins ..............5-3 Processor Microarchitecture ............5-3 SYSCON Programming .............. 5-11 Bus Width ................5-14 Slow Device Protocol ............. 5-14 Pipelined Protocol ..............5-15 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 10 Backoff ................5-50 SDRAM INTERFACE SDRAM I/O Pins ................. 6-7 SDRAM Physical Connection ............6-8 Internal TigerSHARC processor Address and SDRAM Physical Connection ................ 6-11 SDRAM Programming ............... 6-19 SDRAM Control Register (SDRCON) ........6-19 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 11 Bank Active (ACT) Command ..........6-33 Read Command ..............6-34 Bus Width = 64 ..............6-36 Bus Width = 32 ..............6-37 Write Command ..............6-38 Bus Width = 64 ..............6-40 Bus Width = 32 ..............6-41 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 12 Transfer Control Block (TCB) Registers ......7-15 DIx Register ..............7-16 DXx Register ..............7-17 DYx Register ..............7-17 DPx Register ..............7-18 DMA Control and Status Registers ..........7-23 DMA Status Register (DSTAT/DSTATC) ......7-23 DMA Control Registers ............7-26 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 13 DMA Transfers ..............7-33 Internal Memory Buses ............. 7-33 DMA Channels ..............7-34 DMA Memory Accesses ............7-34 DMA Channel Prioritization ..........7-36 Internal Memory Bus Priority ..........7-36 DMA Channel Priority ............. 7-36 ADSP-TS101 TigerSHARC Processor xiii Hardware Reference...
Page 14 External Port DMA Transfer Types ........7-51 External to Internal Memory ..........7-51 Internal to External Memory ..........7-54 External I/O Device to External Memory (Flyby) ....7-55 External Memory to External I/O Device (Flyby) ....7-57 DMA Semaphores ............7-59 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 15 Reset and Boot ................ 8-7 Link Port Communication Protocol ..........8-8 Transmission Delays ..............8-15 Error Detection Mechanisms ............8-17 Transmitter Error Detection ..........8-18 Receiver Error Detection ............8-18 Control Register (LCTLx) ............8-19 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 16 JTAG Functionality ..............9-12 Pins ..................9-12 JTAG Instruction Register ............. 9-14 Data Registers ............... 9-14 SYSTEM DESIGN Overview ..................10-1 TigerSHARC Processor Pins ............10-3 Pin Definitions ..............10-4 Strap Pin Function Descriptions ..........10-7 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 17 General Boot Scenario ............10-19 No Boot Mode ..............10-20 Booting a Single TigerSHARC Processor ......10-20 EPROM/Flash Device Boot ..........10-20 Host Boot ............... 10-22 Link Port Boot ..............10-24 Booting a Multiprocessor System ......... 10-26 ADSP-TS101 TigerSHARC Processor xvii Hardware Reference...
Page 18 Resources and References ............10-38 Decoupling Capacitors and Ground Plane Recommendations 10-38 Signal Integrity ..............10-39 IBIS Models ..............10-39 Output Pin Drive Strength Control ........ 10-39 ADSP-TS101 Processor EZ-KIT Lite ......10-40 Recommended Reading References ........10-40 xviii ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 19: Preface
For programming informa- tion, see the ADSP-TS101 TigerSHARC Processor Programming Reference. For timing, electrical, and package specifications, see the ADSP-TS101 TigerSHARC Embedded Processor Data Sheet.
Page 20: Manual Contents
TigerSHARC pro- cessor initiates. • “Interrupts” This chapter discusses the various types of interrupts supported by the TigerSHARC processor. Some of the interrupts are generated internally or externally. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 21 This chapter describes system features of the TigerSHARC proces- sor. These include Power, Reset, Clock, JTAG, and Booting, as well as pin descriptions and other system level information. This hardware reference is a companion document to the ADSP-TS101 TigerSHARC Processor Programming Reference. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 22: Additional Literature
• ADSP-TS101 TigerSHARC Processor Programming Reference What’s New in This Manual This is the first revision of the ADSP-TS101 TigerSHARC Processor Hard- ware Reference. In future revisions, this section will document additions and corrections from previous revisions of the book.
Page 23: Processor Family
Preface • Contact your local Analog Devices sales office or an authorized Analog Devices distributor • Send questions by mail to: Analog Devices, Inc. DSP Division One Technology Way P.O. Box 9106 Norwood, MA 02062-9106 Processor Family The name TigerSHARC refers to the family of Analog Devices 32-bit, floating-point digital signal processors (DSP).
Page 24: Product Related Documents
Product Information You may also obtain additional information about Analog Devices and its products by: • FAXing questions or requests for information to 1-781-461-3010 (North America) or 089/76 903-557 (Europe Headquarters) • Accessing the Digital Signal Processing Division FTP site: ftp ftp.analog.com or ftp 137.71.23.21 or...
Page 25: Printed Manuals
Customer Service representative. The manuals can be purchased only as a kit. For additional information, call 1-603-883-2430. If you do not have an account with Analog Devices, you are referred to Analog Devices distributors. To get information on our distributors, log on to http://www.analog.com/world/corp_fin/sales_directory/...
Page 26: Hardware Manuals
Data Sheets All data sheets can be downloaded from the Analog Devices Web site. As a general rule, any data sheets with a letter suffix (L, M, N, S) can be obtained from the Literature Center at 1-800-ANALOGD (1-800-262-5643) or down loaded from the Web site.
Page 27: Conventions
0101 between each four digit group. This symbol indicates a note that provides supplementary information on a related topic. In the online version of this book, the word Note appears instead of this symbol. ADSP-TS101 TigerSHARC Processor xxvii Hardware Reference...
Page 28 Warning appears instead of this symbol. LSB, MSB Abbreviations for Least Significant Bit and for Most Significant Bit. LSW, MSW Abbreviations for Least Significant Word and for Most Significant Word. xxviii ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 29: Introduction
A separate document, the ADSP-TS101 TigerSHARC Processor Programming Reference, contains the instruction set description required for programming the TigerSHARC processor. In addition to this manual, designers should refer to the ADSP-TS101 TigerSHARC Embedded Proces- sor Data Sheet for pin descriptions, and timing, electrical, and package specifications.
Page 30 As shown in Figure 1-1 and Figure 1-2, the processor has the following architectural features: • Dual computation blocks—X and Y—each consisting of a multi- plier, ALU, shifter, and a 32-word register file • Dual integer ALUs—J and K—each containing a 32-bit IALU and 32-word register file ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 31 • Three 128-bit buses providing high bandwidth connectivity between all blocks • External port interface including the host interface, SDRAM con- troller, static pipelined interface, four DMA channels, four link ports (each with two DMA channels), and multiprocessing support ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 32 • Simple, orthogonal instruction allowing the compiler to efficiently use the multi-instruction slots • General-purpose data and IALU register files • 32- and 40-bit floating-point and 8-, 16-, 32-, and 64-bit fixed- point native data types ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 33 RESET JTAG Figure 1-3. Single Processor Configuration • Large address space • Immediate address modify fields • Easily supported relocatable code and data • Fast save and restore of processor registers onto internal memory stacks ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 34: Dsp Architecture
High performance is facilitated by the ability to execute up to four 32-bit wide instructions per cycle. The TigerSHARC processor uses a variation of a Static Superscalar™ architecture to allow the programmer to specify ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 35 While the core processor is doing the above, the DMA channels can be replenishing the internal memories in the background with quad data from either the external port or the link ports. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 36: Compute Blocks
Figure 1-5: • Fixed-point format These include 64-bit long-word, 32-bit normal word, 16-bit short word, and 8-bit byte word. For short word fixed-point arithmetic, ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 37: Arithmetic Logic Unit (Alu)
(CLU). The CLU instructions are designed to support different algorithms used for commu- nications applications. The algorithms that are supported by the CLU instructions are: • Viterbi Decoding • Turbo-code Decoding • De-spreading for code-division-multiple-access (CDMA) systems ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 38 1 The TigerSHARC processor internal data buses are 128 bits (one quad-word) wide. In a quad-word, the DSP can move 16 byte words, 8 short words, 4 normal words, or 2 long-words over the bus at the same time. 1-10 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 39: Multiply Accumulator (Multiplier)
(which is internal to the shifter) BFOTMP • Bit FIFO operations to support bit streams with fields of varying length For more information on the shifter, see “Shifter Registers” on page 2-13. ADSP-TS101 TigerSHARC Processor 1-11 Hardware Reference...
Page 40: Integer Arithmetic Logic Unit (Ialu)
Fourier transformations. The TigerSHARC pro- cessor circular buffers automatically handle address pointer wraparounds, reducing overhead and simplifying implementation. 1-12 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 41: Program Sequencer
(register dependency check). Up to two compu- tation instructions per compute block can be issued in each cycle, instructing the ALU, multiplier, or shifter to perform independent, simul- taneous operations. ADSP-TS101 TigerSHARC Processor 1-13 Hardware Reference...
Page 42: Quad Instruction Execution
The TigerSHARC processor can execute up to four instructions per cycle from a single memory block, due to the 128-bit wide access per cycle. The ability to execute several instructions in a single cycle derives from a Static 1-14 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 43: Relative Addresses For Relocation
This fast save/restore capability permits effi- cient interrupts and fast context switching. It also allows the TigerSHARC processor to dispense with on-chip PC stack or alternate registers for regis- ter files or status registers. ADSP-TS101 TigerSHARC Processor 1-15 Hardware Reference...
Page 44: Internal Memory And Other Internal Peripherals
These buses are 128 bits wide to allow up to four instructions, or four aligned data words, to be transferred in each cycle on each bus. On-chip system elements also use these buses to access memory. 1-16 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 45: Internal Transfer
(DAB) automatically aligns quad-words that are not aligned in memory. A memory quad-word is comprised of four 32-bit words or 128 bits of data. A memory long-word is comprised of two 32-bit words or 64 bits of data. ADSP-TS101 TigerSHARC Processor 1-17 Hardware Reference...
Page 46: Scalability And Multiprocessing
I/O requirements since it allows the I/O to occur without degrading core processor performance. Scalability and Multiprocessing The TigerSHARC processor, like the related Analog Devices product the SHARC processor, is designed for multiprocessing applications. The pri- mary multiprocessing architecture supported is a cluster of up to eight TigerSHARC processors that share a common bus, a global memory, and an interface to either a host processor or to other clusters.
Page 47: External Port
On-chip decoding of high order address lines (to generate memory block select signals) facilitates addressing of external memory devices. Separate control lines are also generated for simplified addressing of page mode DRAM. ADSP-TS101 TigerSHARC Processor 1-19 Hardware Reference...
Page 48: Multiprocessing
TigerSHARC proces- sors and a host processor. • Bus arbitration rotates, except for host requests that always hold the highest priority. • Processor bus lock allows indivisible read-modify-write sequences for semaphores. 1-20 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 49: Host Interface
TigerSHARC pro- cessor and can access the DMA channel setup. Vector interrupt support is provided for efficient execution of host commands and burst-mode transfers. ADSP-TS101 TigerSHARC Processor 1-21 Hardware Reference...
Page 50: Dma Controller
Asynchronous off-chip peripherals can control any one of four DMA channels using DMA request lines ( ). Other DMA features DMAR3–0 include flyby (for channel 0 only), interrupt generation upon completion of DMA transfers, and DMA chaining for automatically linked DMA transfers. 1-22 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 51: Link Ports
64-bit period register and the count resumes immediately. Clock Domains There are two major clock domains in the TigerSHARC processor, driven by two input clocks—the local clock ( ) and the system clock ( LCLK SCLK ADSP-TS101 TigerSHARC Processor 1-23 Hardware Reference...
Page 52: Booting
Booting The AC specification and bus interface are defined in reference to the . (See the ADSP-TS101 TigerSHARC Embedded Processor Data Sheet SCLK for the full AC specification.) The internal is phase locked to the SCLK input by a Phase Locked Loop (PLL).
Page 53: Programming Model
Introduction Programming Model Refer to the ADSP-TS101 TigerSHARC Processor Programming Reference for more detailed information. ADSP-TS101 TigerSHARC Processor 1-25 Hardware Reference...
Page 54 Programming Model 1-26 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 55: Memory And Register Map
This chapter describes the TigerSHARC processor memory and register map. For information on using registers for computations and memory for register loads and stores, see the ADSP-TS101 TigerSHARC Processor Pro- gramming Reference. For information on using registers for configuring the TigerSHARC processor’s peripherals use the applicable chapters in this...
Page 56: Host Address Space
When referring to this space, the pipelined or asynchronous protocol is used according to the host bits in the register—for SYSTAT additional information on the register see Figure 2-9 on SYSTAT SYSTATCL ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 57 PROCESSOR ID 0 0x0008 FFFF 0x0200 0000 INTERNAL MEMORY BROADCAST BLOCK 1 0x0008 0000 0x01C0 0000 RESERVED RESERVED 0x0000 FFFF 0x003F FFFF INTERNAL MEMORY INTERNAL MEMORY BLOCK 0 0x0000 0000 0x0000 0000 Figure 2-1. Global Memory Map ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 58: External Memory Bank Space
, where the access protocol is user configurable as pipelined or slow device protocol, and the parameters are defined by the register value—see section “Bus SYSCON Control/Status (BIU) Register Group” on page 2-30. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 59: Multiprocessor Space
Broadcast space allows write access to all Tig- erSHARC processors in the cluster. Each TigerSHARC processor in the cluster is identified by its ID. Valid processor ID values are 0 through 7. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 60: Internal Address Space
Internal address space is used to access the internal memory blocks, or any of the Universal registers (Uregs). Universal registers are internal registers that are mapped to the TigerSHARC processor memory map. Most soft- ware accessible registers are Uregs. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 61: Internal Memory Access
DSPs in a multiprocessor cluster. Merged and Broadcast Distribution are internal access methods. For additional information on memory access methods, see “IALU” in the ADSP-TS101 TigerSHARC Processor Program- ming Reference. “Merged Access” on page 2-11 also provides additional information regarding these access modes.
Page 62: Broadcast Write
Y. Broadcast Distribution In Broadcast Distribution, one instruction loads the same data into two compute blocks in the same TigerSHARC processor. Broadcast distribu- tion works with normal, long, or quad data accesses. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 63: Data Alignment Buffer
Register groups are defined in the range 0x3F–0 (63– 0), where groups 0x1F–0 are accessible by all transfer instructions (load immediate, move register, load and store), and groups 0x3F–0x20 are accessible only by move register instructions and direct accesses of other masters. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 64: Compute Block Register Files
Some groups point to compute block X and some to block Y; those that point to both compute blocks in parallel actually point to the same register. 2-10 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 65: Merged Access
For broadcast transfer, the same data is written to simulta- neously. Broadcast duplicates the data from memory to both compute blocks and can only be used for write-to-compute registers. For more information refer to the ADSP-TS101 TigerSHARC Processor Programming Reference. ADSP-TS101 TigerSHARC Processor 2-11...
Page 66: Unmapped Compute Block Registers
(Uregs), in that they are not accessed in the same way that Uregs are accessed. These registers are accessed by regular compute block instructions that transfer the data between the unmapped registers and the general-purpose compute block Uregs. 2-12 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 67: Global Registers-Xstat/Ystat Compute Block Status Registers
ALU Registers The Parallel Results registers ( ) are two 32-bit registers used for sideways sum instructions. For more information regarding the registers, see “ALU” in the ADSP-TS101 TigerSHARC Processor Program- ming Reference. Multiplier Registers The Multiplier Results registers ( ) are used as accumulators MR3–0...
Page 68: Ialu Registers
Group Definition Group 0x180180 – 0x18019F J-IALU register file 0x0C 0x1801A0 – 0x1801BF K-IALU register file 0x0D 0x1801C0 – 0x1801DF J-IALU circular buffer register 0x0E file 0x1801E0 – 0x1801FF K-IALU circular buffer register 0x0F file 2-14 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 69: Register J31 - Jstat
. When used as an operand in an IALU arithmetic, logical, or function operation — are treated as zero. See the IALU chapter of the ADSP-TS101 TigerSHARC Processor Programming Reference. Table 2-7. JSTAT Register Bit Descriptions Bits...
Page 70: Sequencer Control Register - Sqctl
Register Access Features For more information regarding the sequencer registers, see “Program Sequencer” in the ADSP-TS101 TigerSHARC Processor Programming Reference. Sequencer Control Register – SQCTL The sequencer is controlled and configured by writing to the regis- SQCTL ter, which is set to 0x0100 after reset.
Page 71 Direct Remarks Word Memory Address Address branch (see Instruction in the 0x180340 CJMP CJUMP ADSP-TS101 TigerSHARC Processor Programming Reference) Address for return from interrupt (see the 0x180342 RETI ADSP-TS101 TigerSHARC Processor Programming Reference) Alias of for nesting interrupts RETIB RETI (see “Interrupts”...
Page 72 Reset value 0xFF04 Static condition flag register 0x18035C SFREG low clear—used to clear 0x18035E Write only ILATCLL ILAT ILAT register high clear—used to clear 0x18034F Write only ILATCLH ILAT ILAT register 1 According to strap. IRQEN 2-18 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 73: Ilat Registers
(See the SFREG ADSP-TS101 TigerSHARC Processor Programming Reference for informa- tion about how this register is updated and used). ILAT Registers register is a single 64-bit register accessed as two 32-bit registers ILAT .
Page 74: Interrupt Vector Table Register Groups
DMA #4 Reg 0x180716 IVDMA4 DMA #5 Reg 0x180717 IVDMA5 DMA #6 Reg 0x180718 IVDMA6 DMA #7 Reg 0x180719 IVDMA7 DMA #8 Reg 0x18071D IVDMA8 DMA #9 Reg 0x18071E IVDMA9 DMA #10 Reg 0x18071F IVDMA10 2-20 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 75: Debug Register Groups
2-23. The debug registers can only be accessed as single-word registers. In emulation mode the debug registers can be accessed only by move, register-to-register, or immediate data load instructions. These registers cannot be loaded from or stored to memory directly. ADSP-TS101 TigerSHARC Processor 2-21 Hardware Reference...
Page 76 Cycle counter high 0x180365 Reset value 0x01 CCNT1 Performance monitor counter 0x180366 Reset value 0x0 PRFCNT Trace buffer mask 0x180370 Read only, reset value 0xFFFFFF00 TRCBMASK Trace buffer pointer 0x180378 Read only, reset value0x0 TRCBPTR 2-22 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 77: Performance Monitor Counter - Prfcnt
Bit31 indicates if the events in the same cycle are summed or ORed. The entire register is cleared after reset. The bit descriptions for this register are shown in Figure 2-2 on page 2-24 and Figure 2-3 on page 2-25. ADSP-TS101 TigerSHARC Processor 2-23 Hardware Reference...
Page 78 Figure 2-3 BUS1 Transaction types Figure 2-2. PRFM (Upper) Register Bit Descriptions 1 Monitoring is performed on transactions driven on bus n (n is 0, 1, or 2), including virtual bus trans- actions 2-24 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 79: Watchpoint Control - Wp0Ctl, Wp1Ctl And Wp2Ctl
Each of the three watchpoints has a control register used to define its operation. After reset, the operating mode is in “watchpoint disabled” (state 00). The bit descriptions for this register are shown in Figure 2-4 on page 2-26 and Figure 2-5 on page 2-27. ADSP-TS101 TigerSHARC Processor 2-25 Hardware Reference...
Page 80 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNTER Watchpoint counter installation Figure 2-4. WPxCTL (Upper) Register Bit Descriptions 2-26 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 81: Watchpoint Status - Wp0Stat, Wp1Stat And Wp2Stat
Each of the three watchpoints has a status register used to indicate its operation. After reset, the field is in “watchpoint disabled” (state 00). The bit descriptions for this register are shown in Figure 2-6 on page 2-28 and Figure 2-7 on page 2-29. ADSP-TS101 TigerSHARC Processor 2-27 Hardware Reference...
Page 82 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved EX Watchpoint executing Watchpoint disable Searching for match Watchpoint count expired Figure 2-6. WPxSTAT (Upper) Register Bit Descriptions 2-28 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 83: Cycle Counters - Ccnt0 And Ccnt1
9-9. Watchpoint Address Pointers – WP0L, WP1L, WP2L, WP0H, WP1H and WP2H The watchpoint address pointers are 32-bit pointers defining the address, or address range, of the watchpoints. Their value after reset is undefined. ADSP-TS101 TigerSHARC Processor 2-29 Hardware Reference...
Page 84: External Port Registers
• Link Port Receive/Transmit DMA registers • DMA Control and Status registers • Link Port Control and Status registers • Link Port Buffer registers Bus Control/Status (BIU) Register Group The Bus Control/Status registers are defined in the following sections. 2-30 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 85: Systat/Systatcl Register
Figure 2-8 on page 2-32 and Figure 2-9 on page 2-33. • – no change in register contents SYSTAT • – error Bits19–16 are cleared after the read SYSTATCL ADSP-TS101 TigerSHARC Processor 2-31 Hardware Reference...
Page 86 AutoDMA ERROR Set when data is written to AutoDMA while the corresponding AutoDMA channel is not initialized SLAVE BR. READ Broadcast read ‘by another master’ error indication Figure 2-8. SYSTAT/SYSTATCL (Upper) Register Bit Descriptions 2-32 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 87 Set) sequence is completed (in ID=0 only)–indicates that it is legal to access SDRAM BUSLOCK ACTIVE Bus lock bit is set and the bus is held by the TigerSHARC processor Reserved Figure 2-9. SYSTAT/SYSTATCL (Lower) Register Bit Descriptions ADSP-TS101 TigerSHARC Processor 2-33 Hardware Reference...
Page 88: Syscon Register (Dma 0X180480)
(if slow bit is cleared) 00 – One cycle pipe depth 01 – Two cycles pipe depth 10 – Three cycles pipe depth 11 – Four cycles pipe depth Figure 2-10. SYSCON (Upper) Register Bit Descriptions 2-34 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 89 00 – Zero wait cycle 01 – One wait cycle 10 – Two wait cycles 11 – Three wait cycles Bit 16 continued on Figure 2-10 HOST PIPE DEPTH BITS Figure 2-11. SYSCON (Lower) Register Bit Descriptions ADSP-TS101 TigerSHARC Processor 2-35 Hardware Reference...
Page 90: Sdrcon (Sdram Configuration) (Dma 0X180484)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved Bit15 continued on Figure 2-13 Figure 2-12. SDRCON (Upper) Register Bit Descriptions The bit descriptions for this register are shown in Figure 2-12 on page 2-36 and Figure 2-13 on page 2-37. 2-36 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 91 011 – Five cycles INIT SEQUENCE Initialization sequence 1 – cycle follows refresh in the SDRAM initialization sequence 0 – precedes refresh Bits 31-16 continued on Figure 2-12 Reserved Figure 2-13. SDRCON (Lower) Register Bit Descriptions ADSP-TS101 TigerSHARC Processor 2-37 Hardware Reference...
Page 92: Buslk System Control
Bits15 to 1 continued on Figure 2-15 Figure 2-14. BUSLK (Upper) Register Bit Descriptions The bit descriptions for this register are shown in Figure 2-14 on page 2-38 and Figure 2-15 on page 2-39. 2-38 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 93: Bmax Current Value
See “Bus Fairness — BMAX” on page 5-47 for more information. The bit descriptions for this register are shown in Figure 2-16 on page 2-40 and Figure 2-17 on page 2-41. ADSP-TS101 TigerSHARC Processor 2-39 Hardware Reference...
Page 94 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved Figure 2-16. BMAX (Upper) Register Bit Descriptions 2-40 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 95: External Port Configuration And Status Registers
1 Can be written only once after hardware reset. After first write, it becomes a read-only register. DMA Registers The DMA register groups are described in Table 2-15 on page 2-43 to Table 2-19 on page 2-46. The DMA registers are only accessible via quad-word accesses. ADSP-TS101 TigerSHARC Processor 2-41 Hardware Reference...
Page 96 “0” to the desired bit location. To retain the bit’s original value, write a logic “1”. See “Direct Memory Access” on page 7-1 for complete DMA register definitions. 2-42 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 97: External Port Dma Register
2 DMA registers can be accessed only as quad-words. AutoDMA Registers The AutoDMA registers are used to implement a slave mode DMA (see “Direct Memory Access” on page 7-1). These registers can only be accessed through multiprocessing memory. ADSP-TS101 TigerSHARC Processor 2-43 Hardware Reference...
Page 98: Autodma0 Register
DMA channel 13 transfers the written data into the internal memory address programmed in the DMA. This register cannot be read, and can only be written through the multiprocessing address space. If the DMA is not initialized, the data is lost. 2-44 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 99: Link Port Transmit Dma Register
0x180443 0x0000 0000 DMA channel 9 0x180444 0x5780 0000 0x180445 0x0000 0000 0x180446 0x0100 0004 0x180447 0x0000 0000 DMA channel 10 0x180448 0x5780 0000 DC10 0x180449 0x0000 0000 0x18044A 0x0100 0004 0x18044B 0x0000 0000 ADSP-TS101 TigerSHARC Processor 2-45 Hardware Reference...
Page 100: Dma Control And Status Register
DMA control register set bits 0x180464 DCNTST DMA control register clear bits 0x180468 DCNTCL DMA status register 0x18046C - F DSTAT Read only DMA status register clear bits 0x180470 - 3 DSTATC Read only 2-46 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 101: Link Registers
Read only LSTAT3 Link # 0 status clear register 0x1804F8 LSTATC0 Link # 1 status clear register 0x1804F9 LSTATC1 Link # 2 status clear register 0x1804FA LSTATC2 Link # 3 status clear register 0x1804FB LSTATC3 ADSP-TS101 TigerSHARC Processor 2-47 Hardware Reference...
Page 102: Link Port Receive And Transmit Buffers
Link # 2 Tx register 0x1804B0-3 – LBUFTX2 Link # 2 Rx register 0x1804B4-7 Read only LBUFRX2 Link # 3 Tx register 0x1804B8-B – LBUFTX3 Link # 3 Rx register 0x1804BC-F Read only LBUFRX3 2-48 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 103: Core Controls
The TigerSHARC processor has two primary clock inputs—local clock ) and system clock ( ). These clocks must receive the same input LCLK SCLK (tie the pins together). These clock signals can be the SCLK_P LCLK_P ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 104: Operation Modes
The cluster bus signals are SCLK specified in the ADSP-TS101 TigerSHARC Embedded Processor Data Sheet with respect to this clock. is the input clock to an Analog Phase Locked Loop (PLL) that LCLK generates the internal clock .
Page 105: Emulation Mode
( In emulation mode, the debug registers (Ureg group 0x1B) can be accessed only by move register-to-register or immediate data load instruc- tions. These registers cannot be loaded from or stored to memory directly. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 106: Supervisor Mode
For more information, see “Sequencer NMOD SQCTL Control Register – SQCTL” on page 2-16. • An interrupt routine is executed—indicated by non-zero PMASK For more information, see “PMASK Register” on page 4-13.) ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 107: User Mode
All other registers cannot be written by the core program in user mode. An attempt to write to a protected register causes an exception. These regis- ters can still be accessed by another master (DMA, external host, and so on). ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 108: Low Power Mode
2 is executed. To check that all the transactions are complete and to ensure that the OFIFO and IFIFO are empty, initiate a write to an internal address via the ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 109: Multiprocessing Systems
SHARC processors they can enter low power. The indication can be sent through an interrupt, flag pin, or a write transaction on the cluster bus. After this transaction, the LPD can no longer access the other processors in the system. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 110: Return To Normal Operation
SQSTAT ister. (See “Sequencer Status Register – SQSTAT” on page 2-16.) After power up reset, are inputs where static 100KΩ pull-downs hold FLAG(3-0) them at zero value. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 111: Timers
Whenever the timer count reaches zero, the timer issues the two timer expire interrupts (high and low priority), reinitializes the counter to the initial value, and starts running again. If the timer is active ( bit is TMRIRN ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 112: Timer 0 Output Pin
INxx the timer (when value is copied again to the timer). TMRINxx Timer 0 Output Pin indicates Timer 0 expire and issues a pulse on the timer out pin TMR0E for four cycles. SCLK 3-10 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 113 The first instruction of the interrupt routine is inserted into the instruction flow after it has occurred. From this point, the instructions that are already in the pipeline complete their execution. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 114: Interrupts
DMA is initialized to load the boot data into memory address 0x0. When the boot DMA is executed, it issues a DMA interrupt. The DMA interrupt vector is also initialized to address 0x0. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 115: Interrupt Types
• Level-sensitive interrupt requests must be sustained until serviced, otherwise they are not seen. If the request continues after being ser- viced, it is considered a new interrupt. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 116: Interrupts Generated By On-Chip Modules
Only one bit is cleared when the interrupt rou- tine is served. If both high and low priority interrupts are enabled, the interrupt is serviced twice. The assumption is that only one of the inter- rupts is enabled. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 117: Link Interrupts
• – interrupt priority 22; edge-triggered IVDMA4 • – interrupt priority 23; edge-triggered IVDMA5 • – interrupt priority 24; edge-triggered IVDMA6 • – interrupt priority 25 edge-triggered IVDMA7 • – interrupt priority 29; edge-triggered IVDMA8 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 118: Interrupt Pins (Irq)
The interrupt type is edge- or level-triggered according to SQCTL pro- gramming. See “Sequencer Control Register – SQCTL” on page 2-16. After reset, the interrupts are disabled, unless strap option (on IRQEN ) is used. Vectors are initialized for boot purposes. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 119: Vector Interrupt (Virpt)
This interrupt is issued when the bus lock bit in the register is set SQCTL and the TigerSHARC processor becomes the bus master. This interrupt is used to indicate that the TigerSHARC processor has locked the external bus. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 120: Hardware Error Operations
Refer to “Error Detection Mechanisms” on page 8-17. For additional information refer to “Status Register (LSTATx)” on page 8-23). After reset, the hardware error interrupt is disabled and vectors are not initialized. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 121: Software Exceptions
• Illegal operations: – Undefined instruction (not on all cases) – Illegal combination of instructions, described in the “Instruction Flow” chapter of the ADSP-TS101 TigerSHARC Processor Program- ming Reference • External access to an illegal space – multiprocessing broadcast read...
Page 122: Emulation Debug
Emulation mode can be caused by: • An instruction EMUTRAP • A watchpoint match (when programmed to cause an emulation trap) • A JTAG emulation activation During and after reset, the emulation trap is enabled. 4-10 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 123: Other Interrupt Registers
). Such a write ANDs the data written with the old data of the ILATCLH register. In this case, a zero bit in the input data clears the corre- ILAT sponding bit in , while a set bit keeps it unchanged. This way, an ILAT ADSP-TS101 TigerSHARC Processor 4-11 Hardware Reference...
Page 124: Imask Register
Consequently, the order IMASK of the interrupt bits is identical to those found in the register. Bit60 ILAT is a global hardware interrupt enable. When cleared, no interrupts, except for exception and emulation, are enabled. 4-12 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 125: Pmask Register
(see “if cond, RTI (ABS)” and “if cond, RDS” in the ADSP-TS101 TigerSHARC Processor Programming Reference). When the is nonzero, all the interrupts with a lower or equal prior-...
Page 126: Interrupt Service
ILAT IMASK . If the global interrupt enable bit is set and the result of the PMASK_R ILAT is not zero, the highest priority interrupt that is IMASK PMASK_R enabled is served. 4-14 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 127 4. The return PC (which points to the instruction that would have been executed had the interrupt not occurred) is saved in the appropriate register— for a hardware interrupt, for a RETI RETS software interrupt, and for an emulation debug. DBGE ADSP-TS101 TigerSHARC Processor 4-15 Hardware Reference...
Page 128 2. Once masks are set: • is embedded in , that is, if is set PMASK60 PMASK_R PMASK60 then = 0...0 PMASK_R50–0 • Exceptions and emulation conditions are not affected by PMASK60 IMASK60 • Insert ISR fetch address 4-16 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 129 JUMP TO RETI ISR@EX2 IS IMASK[60] AND NOT PMASK[60] RESTORE RETIB: SETS PMASK[60] ILAT[N] CLEARED RESTORE CONTEXT PMASK[N] SET PMASK[60] SET IF NESTING: STORE CONTEXT STORE RETIB: EXECUTE ISR CLEARS PMASK[60] Figure 4-1. Hardware Interrupts ADSP-TS101 TigerSHARC Processor 4-17 Hardware Reference...
Page 130 5. If nesting, for hardware interrupt and set, the ISR should: PMASK60 • Store context • Store : which automatically clears RETIB PMASK60 Instructions for storing context and have to be specified in RETIB the software. 6. Execute 4-18 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 131: Interrupt Handling
. If you use , you access while RETIB RETI RETIB RETI simultaneously setting or clearing (depending on whether you are PMASK60 writing or reading). ADSP-TS101 TigerSHARC Processor 4-19 Hardware Reference...
Page 132 ISR*/ .var register_store_2; .section program; /*This example shows how to set up nested interrupts using the two timers.*/ Setup_Timer_Interrupts: /*Set up the interrupt service routines in the Interrupt Vector Table*/ 4-20 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 133 = RETIB;; /*Clears Pmask[60], can now jump to higher priority ISRs*/ xr1=r3+r4;; /*Any code for the ISR would go here*/ RETIB = xR0;; /*Sets Pmask[60], can no longer leave ISR for other interrupts*/ ADSP-TS101 TigerSHARC Processor 4-21 Hardware Reference...
Page 134: Returning From Interrupt
RTI (ABS)(NP);; Returning From Interrupt The return from interrupt is performed using the instruction (see “if cond, ” in the ADSP-TS101 TigerSHARC Processor Program- RTI (ABS) ming Reference). The return address should be put in the register RETIB (recommended at about eight cycles beforehand to enable usage).
Page 135: Exceptions
EMUIR case of an emulation exception. • PC is stored in in case of an exception, or in register in RETS DBGE case of an emulation exception. • Instructions are flushed from the pipeline. ADSP-TS101 TigerSHARC Processor 4-23 Hardware Reference...
Page 136 INSERT ISR FETCH ADDRESS STORE PC IN RETS JUMP TO RETI FLUSH INSTRUCTIONS IN PIPE ISR@EX2 STORE RETS IN MEMORY STORE RETI EXECUTE ISR SAVE RETSFROM MEMORY TO RETI RTI; RESTORE RESTI Figure 4-2. Software Exception (Interrupt) 4-24 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 137 • In order to protect the old value before returning you must RETI execute the following instruction lines, then jump to RETS [j31+temporary address] = RETI;; RETI = RETS;; RTI; RETI = [j31+temporary address];; ADSP-TS101 TigerSHARC Processor 4-25 Hardware Reference...
Page 138 Exceptions 4-26 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 139: Cluster Bus
SDRAM chips. The SDRAM is useful for mass storage of the system, since it is possible to build very large memory arrays. The peak data throughput to the SDRAM is one data transfer every clock cycle. The ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 140: External Bus Features
External Bus Features The external bus includes: • Bus width: 64- or 32-bits, configured separately for memory, mul- tiprocessing or host interface • Pipelined transactions with a programmable number of pipeline stages • Programmable IDLE states ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 141: Bus Interface I/O Pins
It can perform as a single processor or in a multiprocessing system on a common external bus (as shown in Figure 5-1 on page 5-6). There may be a host (or host interface) in the system as well, ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 142 I/O devices, memory controllers and other peripherals on the data phase. The TigerSHARC processor can deassert for adding wait states for synchro- nous accesses to its internal memory. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 143 TigerSHARC processor increments the address automatically as long as BRST asserted. where the arbitration between multiple TigerSHARC processors and between TigerSHARC processors and the host is accomplished using a distributed arbitration logic on the TigerSHARC processors themselves. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 144 (OPTIONAL) FLYBY ADDR IOEN DATA LXDAT7–0 LINK MSSD LXCLKIN DEVICES SDRAM (4 MAX) LXCLKOUT MEMORY (OPTIONAL) (OPTIONAL) LXDIR LDQM HDQM SDWE TMR0E SDCKE SDA10 CONTROLIMP2–0 ADDR CONTROL DS2–0 DATA Figure 5-1. Typical Multiprocessing Cluster Configuration ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 145 (DMA or core) on one of the three internal buses. The transaction is strobed by the OFIFO and, in turn, is driven on the external bus. If the transaction is a write transaction, ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 146 ADDR ADDR OFIFO OFIFO DATA DATA IFIFO IFIFO DATA DATA INTERNAL INTERNAL OBUF OBUF DMA CONTROLLER DMA CONTROLLER DMA WRITE - TIGERSHARC BUS MASTER DMA READ - TIGERSHARC BUS MASTER Figure 5-2. External Port Architecture ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 147 Even when more than one bus is not assigned to regular bus transactions, only one virtual bus transaction can be executed in a given cycle. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 148 • IFIFO is full (three or more transactions in the IFIFO). The request priority is high in order to prevent delays on the external bus. In all other cases, the IFIFO request has low priority. 5-10 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 149: Syscon Programming
For each of the three banks there are six mode bits—the fields are shown in Figure 5-3. The setup of these fields is orthogonal—each of the fields can be programmed to a different value. ADSP-TS101 TigerSHARC Processor 5-11 Hardware Reference...
Page 150 (if slow bit is cleared) Figure 5-4 00 – One cycle pipeline depth 01 – Two cycles pipeline depth 10 – Three cycles pipeline depth 11 – Four cycles pipeline depth Figure 5-3. SYSCON (Upper) Register Bit Descriptions 5-12 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 151 01 – One wait cycle 10 – Two wait cycles 11 – Three wait cycles Bit 16 continued on HOST PIPELINE DEPTH BITS Figure 5-3 See Figure 5-3 Figure 5-4. SYSCON (Lower) Register Bit Descriptions ADSP-TS101 TigerSHARC Processor 5-13 Hardware Reference...
Page 152: Bus Width
The internal wait field identifies the number of internal wait cycles on slow accesses. If the number of internal waits is zero, the external wait mechanism cannot be used for these transactions. 5-14 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 153 The address and controls of a transaction are issued on the address cycle and the data is transferred a few cycles later—in the case of TigerSHARC processor, one to four cycles depending on the transac- tion direction and system configuration programming. The TigerSHARC ADSP-TS101 TigerSHARC Processor 5-15 Hardware Reference...
Page 154: Control Signals
If the slave is not ready, it deasserts the signal and delays the data. The exact way the signal behaves is discussed in “Wait Cycles” on page 5-23. 5-16 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 155 Single transactions take a different number of cycles according to transac- tion size and external bus width: • Single transactions: one cycle • Long transactions on 64-bit bus: one cycle • Long transactions on 32-bit bus: two cycles ADSP-TS101 TigerSHARC Processor 5-17 Hardware Reference...
Page 156: Pipelining Transactions
TigerSHARC. Without the signal, this same access would be BRST interpreted as four single-word (i.e., 32-bit normal word) accesses which would result in an illegal register access. 5-18 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 157 BRST lowed by a word write, and then two long writes where the is asserted BRST in the first cycle of each transaction. The pipeline depth is one cycle since these are write transactions. ADSP-TS101 TigerSHARC Processor 5-19 Hardware Reference...
Page 158 TigerSHARC Pipelined Interface SCLK ADDR AA 1 AA 2 QUAD-WORD WORD LONG-WORD LONG-WORD DATA BRST Figure 5-6. Pipelined Transactions – Sequential Writes Pipeline Depth = 1, Bus Width = 32 5-20 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 159 A B1 AB 2 ADDR QUAD-WORD QUAD-WORD DATA BRST DATA SLAVE A DATA SLAVE B Figure 5-7. Burst Read Followed by Burst Read Pipeline Depth = 4, Bus Width = 32, IDLE Bit Set ADSP-TS101 TigerSHARC Processor 5-21 Hardware Reference...
Page 160 IDLE are true. If the difference between the pipeline depths is one, an IDLE cycle is inserted. The second transaction address cycle begins two cycles after the end of the first transaction. 5-22 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 161: Wait Cycles
In regular transactions, if the slave is ready in time for the data cycle of the targeted transactions, the slave asserts the signal in the data cycle. If the slave is not ready, it deasserts the signal on the data cycle and keeps it deasserted until it can continue. ADSP-TS101 TigerSHARC Processor 5-23 Hardware Reference...
Page 162 Here the slave asserts the signal as long as its write buffer has sufficient free slots. See Figure 5-10 on page 5-26. In this example, the address cycle, , triggers the slave to deassert the signal. This 5-24 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 163 This applies to the cycle fol- ADSP-TS101 TigerSHARC Processor 5-25 Hardware Reference...
Page 164 • Centralized logic for the signal • Keep the signal logic in slave very fast—enable drive of signal only after the signal has been driven high in the previous cycle. 5-26 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 165: Slow Device Protocol
MS0-1 select signals. The external memory device used with this protocol should be able to latch the data on the first rising edge of either or the MS0-1 ADSP-TS101 TigerSHARC Processor 5-27 Hardware Reference...
Page 166 The right number of wait cycles to guaran- tee enough data setup time is user configurable. 0 WAIT DATA SCLK ADDR DATA MS1-0 Figure 5-11. Slow Protocol Write With 0 Wait Cycles 5-28 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 167 Cluster Bus 0 WAIT DATA SCLK ADDR DATA MS1-0 Figure 5-12. Slow Protocol Read With 0 Wait Cycles ADSP-TS101 TigerSHARC Processor 5-29 Hardware Reference...
Page 168 The extra wait cycles are repeated until one cycle after the signal has been asserted. See Figure 5-15 on page 5-32 for an example. 5-30 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 169: Eprom Interface
EPROM is a byte address space and is not part of the TigerSHARC pro- cessor memory space. It is limited to 16M bytes (maximum address is = 0). The data is driven on the regular data bus 0xFF FFFF ADDR31–24 Bits7–0. ADSP-TS101 TigerSHARC Processor 5-31 Hardware Reference...
Page 170 Figure 5-15. Slow Protocol Read/Write With External Wait Cycles The TigerSHARC processor uses 16 wait cycles for each read access from the EPROM. During the boot process, the pin is used as the EPROM CS pin until completion. 5-32 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 171 In TigerSHARC processor’s internal or external RAM, the data should be organized as shown in Figure 5-17. After the last boot EPROM bus cycle, there are three IDLE cycles (for slow EPROM disconnect time). ADSP-TS101 TigerSHARC Processor 5-33 Hardware Reference...
Page 172: Flyby Transactions
I/O devices in parallel. Memory is driven in the regular way and the I/O device is controlled with two pins, FLYBY IOEN 5-34 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 173 The data drive, however, is indicated by asserting the IOEN The sequence illustrated in Figure 5-18 applies when: • Transfer is followed by another burst write transfer from I/O to the SDRAM device • Flyby transaction and bus width = 64 ADSP-TS101 TigerSHARC Processor 5-35 Hardware Reference...
Page 174 Write Transfer The sequence illustrated in Figure 5-19 applies when: • Transfer is followed by another burst read transfer from the SDRAM to I/O device • Flyby transaction; latency = 2; bus width = 64 5-36 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 175 Cluster Bus SCLK SDCKE MSSD SDWE A11-0 QUAD-WORD QUAD-WORD DATA MEMORY DRIVE DMARx FLYBY IO EN Figure 5-19. Synchronous Burst Read Transfer ADSP-TS101 TigerSHARC Processor 5-37 Hardware Reference...
Page 176: Multiprocessing
TigerSHARC processor with 2-0 = 0. If is not used, terminate this pin as either pull-up or no connection. If is not used, terminate this pin as ID7-1 pull-up. 5-38 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 177 Provides an indication that the current bus master has locked the bus. Bus Master The current bus master TigerSHARC processor asserts . For debugging only. At reset, this is a strap pin. See the ADSP-TS101 TigerSHARC Embedded Processor Data Sheet for more information. Multiprocessing ID ID2-0 Indicates the TigerSHARC processor’s ID.
Page 178 SDRAM because this processor performs the initializa- tion (Mode Register Set ) of the SDRAM. Also, there are issues related to open drain pull-ups which are only enabled on the pro- cessor with ID=000. 5-40 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 179: Bus Arbitration Protocol
When one of the TigerSHARC processors needs to become a master, it asserts its own line, while at the same time monitoring the other lines. The current master, after completing its transaction, deasserts its ADSP-TS101 TigerSHARC Processor 5-41 Hardware Reference...
Page 180 TURN TURN TURN OVER OVER OVER TS0 IS THE TS1 IS THE TS2 IS THE TS0 IS THE CYCLE CYCLE CYCLE MASTER MASTER MASTER MASTER SCLK Figure 5-20. External Bus Arbitration Sequence, Inactive 5-42 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 181: Core Priority Access (Cpa)
DMA Priority Access (DPA) The DMA Priority Access, , is asserted when a TigerSHARC processor high priority DMA channel accesses external memory—only if is not asserted. This allows a high priority DMA channel belonging to a slave ADSP-TS101 TigerSHARC Processor 5-43 Hardware Reference...
Page 182 The other requesting TigerSHARC processors deassert their when they sense is asserted. When more than one TigerSHARC pro- cessor requests the bus by asserting their s along with , the TigerSHARC processor with the highest priority gains the bus mastership. 5-44 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 183 One cycle is to sense that the priority access is over, the second is to take control of the bus. This is illustrated in Figure 5-22 on page 5-45. ADSP-TS101 TigerSHARC Processor 5-45 Hardware Reference...
Page 184 Figure 5-22 on page 5-45, which shows only one turnover cycle. This is because there are two priority accesses being per- formed. It only takes one turnover cycle to transfer from one priority to another. 5-46 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 185: Bus Fairness — Bmax
Once the bit is cleared, arbi- BUSLK BUSLK tration resumes the regular path. Before accessing a semaphore, the TigerSHARC processor should check whether it is the bus master by read- ADSP-TS101 TigerSHARC Processor 5-47 Hardware Reference...
Page 186: Host Interface
When a transaction to any address space (except the host space) follows a read from the host, the non-host transaction is serialized—for example, the non-host transaction takes place only after all host transactions have completely terminated. This is illustrated in Figure 5-23. 5-48 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 187 • Pipeline depth is always four for read and one for write. • There are IDLE cycle restrictions. • No read from broadcast address space is allowed. • The host must operate with an identical system configuration as other TigerSHARC processors on the cluster bus. ADSP-TS101 TigerSHARC Processor 5-49 Hardware Reference...
Page 188: Backoff
The TigerSHARC processor is designed to yield the bus to the host when the latter asserts , signaling the TigerSHARC processor to yield. BOFF 5-50 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 189 If the semaphore is set when read and the read data is the previous value, there is no need for bus lock on the semaphore access. The host interface can be notified of a bus lock by the pin. BUSLOCK ADSP-TS101 TigerSHARC Processor 5-51 Hardware Reference...
Page 190 Multiprocessing HOST SYSTEM BUS CLUSTER SDRAM SRAM HOST BRIDGE HOST PROCESSOR DSP READ FROM HOST MEMORY HOST READ FROM DSP Figure 5-24. Deadlock Scenario 5-52 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 191 64M words x 32 bits of SDRAM. For SDRAM, all initialization (Mode Register Set) command and configuration is done by processor with ID000. This ID should always be present in any TigerSHARC processor cluster. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 192 TigerSHARC processor one cycle later. latency plus pipeline cycle are maximum four cycles.) (Refer to the timing diagram in the ADSP-TS101 TigerSHARC Embedded Processor Data Sheet.) Pipelining can be used when connecting several SDRAM devices in parallel such that their collective load is too high to be driven by the TigerSHARC processor.
Page 193 SDRCON • CBR Automatic Refresh ( before ) Mode. In this mode, the SDRAM drives its own refresh cycle with no external control input. At cycle end, all SDRAM banks are precharged ( IDLE ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 194 SDRAM device in a low power mode. • t . Active Command time. Required delay between issuing an activate command and issuing a precharge command. A ven- dor-specific value. This option is programmable in the SDRCON register. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 195 SDRAM control, address, and data pins and the TigerSHARC processor's internal Harvard Architecture buses. The internal 32-bit address bus is multiplexed by the SDRAM controller to generate the corresponding chip select, row address, column address, and bank select signals to the SDRAM. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 196 BUSY INT ACK [H:L]DQM [H:L]DQM CORE SDA10 INT MSSD SDRAM ENABLED MSSD 64-BIT A31-0 EXTERNAL PORT A12-0 A1-9,11,12 BUFFERS D63-0 DQ63-0 DELAY BUFFER A11-1 D63-0 Figure 6-1. SDRAM Controller Interface (for a 64-bit Bus Configuration) ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 197: Sdram I/O Pins
SDRAM transactions when is asserted and is LDQM inactive on read transactions. On write transactions, is active when accessing LDQM an odd address word on a 64-bit memory bus to disable the write of the low word. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 198: Sdram Physical Connection
The data bus is either the full 64 bits or the bottom 32 bits according to the memory bus width pro- gramming in (see “SYSCON Programming” on page 5-11). The SYSCON ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 199 The control signals are specific SDRAM control signals. These signals are listed below. • – SDRAM Chip Select MSSD • – Row Address Strobe • – Column Address Strobe • – SDRAM Write Enable SDWE • – Data Mask for Low Word (data Bits31–0) LDQM ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 200 Another option to reduce the load is to buffer the address and control sig- nals in registers to delay these signals in a cycle. In this case the pipeline depth bit in should be set. SDRCON 6-10 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 201: Connection
64-BIT HOST PROM BOOT 64-BIT WIDE BUS FOR SDRAM ACCESSES ONLY ADDRESS PINS CONNECTION (ADSP-TS101 TO EXTERNAL DATA) = A1>A0 CONFIGURED IN SYSCON BUS WIDTH SETTINGS Figure 6-2. External Port Data Align for 64-bit ADSP-TS101 TigerSHARC Processor 6-11 Hardware Reference...
Page 202 32-BIT NORMAL WORD (EVEN AND ODD) 32-BIT HOST PROM BOOT 32-BIT WIDE BUS FOR SDRAM ACCESSES ONLY ADDRESS PINS CONNECTION (ADSP-TS101): EXTERNAL DATA = A0>A0 CONFIGURED IN SYSCON BUS WIDTH SETTINGS Figure 6-3. External Port Data Align for 32-bit 6-12 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 203 Physical Bank Active Cycle Column Access Cycle Physical SDRAM Pin TigerSHARC Internal Address Internal Address Processor Pin SDA10 Zero A10/AP Irrelevant Irrelevant A11 or Bank A12 or Bank A13 or Bank A14 or Bank ADSP-TS101 TigerSHARC Processor 6-13 Hardware Reference...
Page 204 Bank Active Cycle Column Access Cycle Physical SDRAM Pin TigerSHARC Internal Address Internal Address Processor Pin Irrelevant Irrelevant SDA10 A10/AP A11 or Bank A12 or Bank A13 or Bank A14 or Bank A15 or Bank 6-14 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 205 Bank Active Cycle Column Access Cycle Physical SDRAM Pin TigerSHARC Internal Address Internal Address Processor Pin Irrelevant Irrelevant SDA10 Zero A10/AP A11 or Bank A12 or Bank A13 or Bank A14 or Bank A15 or Bank ADSP-TS101 TigerSHARC Processor 6-15 Hardware Reference...
Page 206 Physical Bank Active Cycle Column Access Cycle Physical SDRAM Pin TigerSHARC Internal Address Internal Address Processor Pin SDA10 Zero A10/AP Irrelevant Irrelevant A11 or Bank A12 or Bank A13 or Bank A14 or Bank 6-16 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 207 Bank Active Cycle Column Access Cycle Physical SDRAM Pin TigerSHARC Internal Address Internal Address Processor Pin Irrelevant Irrelevant SDA10 Zero A10/AP A11 or Bank A12 or Bank A13 or Bank A14 or Bank A15 or Bank ADSP-TS101 TigerSHARC Processor 6-17 Hardware Reference...
Page 208 Physical Bank Active Cycle Column Access Cycle Physical SDRAM Pin TigerSHARC Internal Address Internal Address Processor Pin SDA10 Zero A10/AP Irrelevant Irrelevant A11 or Bank A12 or Bank A13 or Bank A14 or Bank 6-18 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 209: Sdram Programming
Device Engineering Council (JEDEC) specifications. In order to support multiple vendors, the TigerSHARC processor register can be pro- SDRCON grammed to meet these requirements. Figure 6-4 on page 6-20 and Figure 6-5 on page 6-21 show the SDRAM control register. ADSP-TS101 TigerSHARC Processor 6-19 Hardware Reference...
Page 210 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved Bits 15 to 31 Figure 6-4. SDRCON (Upper) Register Bit Descriptions 6-20 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 211 See Figure 6-4 Figure 6-5. SDRCON (Lower) Register Bit Descriptions register of the TigerSHARC processor stores the configuration SDRCON information of the SDRAM interface. Writing configuration parameters initiates commands to the SDRAM that take effect immediately. ADSP-TS101 TigerSHARC Processor 6-21 Hardware Reference...
Page 212: Sdram Enable
SDRAM operation with the processor's ability to latch the data output. latency does not apply to write cycles. Bits2–1 in the register select the latency value as SDRCON follows. 00 = 1 cycle latency 6-22 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 213: Setting The Sdram Buffering Option (Pipeline Depth)
16M x 32-bit words. In this example, 0xA and 0xB output from the registered buffers are the same signal, but are buffered separately. In the registered buffers, a delay of one clock cycle occurs between the input (Ix) and its corresponding output (0xA or 0xB). ADSP-TS101 TigerSHARC Processor 6-23 Hardware Reference...
Page 214 A13-0 A13-0 AB13-0 SDRAM #4 SDRAM #8 4M X 4 X 4 4M X 4 X 4 DATA31-0 15-12 31-28 DATA3-0 DATA3-0 A13-0 A13-0 Figure 6-6. Uniprocessor System With Multiple SDRAM Devices (32-bit Bus) 6-24 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 215: Selecting The Sdram Page Size (Page Boundary)
(precharge to delay) defines the required delay, in num- ber of system clock cycles ( ), between the time the SDRAM controller SCLK issues a command and the time it issues an command. ADSP-TS101 TigerSHARC Processor 6-25 Hardware Reference...
Page 216 SDRCON in Table 6-9. Table 6-9. RAS to Precharge Delay (t ) Bits Delay SDRCON Bits13–11 2 cycles 3 cycles 4 cycles 5 cycles 6 cycles 7 cycles 8 cycles 6-26 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 217: Setting The Sdram Power-Up Mode (Init Sequence)
) = 3 cycles (fixed) = = 2 cycles Table 6-10. Data Throughput Rates Accesses Operations Page Throughput per SDRAM Clock (64-bit words) Sequential Uninterrupted Read Same 1 word/1 cycle Non-sequential Uninterrupted Read Same 1 word/1 cycle ADSP-TS101 TigerSHARC Processor 6-27 Hardware Reference...
Page 218: Multiprocessing Operation
The slave processors track the commands that the master processor issues to the SDRAM. This feature or function helps to synchro- nize the SDRAM refresh counters and to prevent needless refreshing operations. 6-28 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 219: Understanding Dqm Operation
In SDRCON a multiprocessing environment, the power up sequence is initiated by the TigerSHARC processor with . Note that software reset does not reset the controller and does not re-initiate a power up sequence. ADSP-TS101 TigerSHARC Processor 6-29 Hardware Reference...
Page 220: Sdram Controller Commands
SDRAM operation parameters by using of the ADDR13–0 SDRAM as data input. The command is issued only by the Tiger- SHARC processor with , and must be issued prior to the first SDRAM access after power up. 6-30 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 221: Precharge (Pre) Command
Table 6-11 below. Table 6-11. Pin State During MRS Command State MSSD SDWE high SDCKE Precharge (PRE) Command command has two functions—terminate a read or write cycle and precharge the active bank. ADSP-TS101 TigerSHARC Processor 6-31 Hardware Reference...
Page 222: Terminating Read/Write Cycles
4. Before the TigerSHARC processor relinquishes the external bus Following a command, the SDRAM cannot accept any other access for the precharge to delay, t . The appropriate field in register should be programmed according to the SDRCON SDRAM characteristics. 6-32 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 223: Bank Active (Act) Command
This is done to keep the page open even if there are occurrences of non-SDRAM accesses within a flow of accesses to a single SDRAM page. Table 6-13. Pin State During ACT Command State MSSD high high SDWE high SDCKE ADSP-TS101 TigerSHARC Processor 6-33 Hardware Reference...
Page 224: Read Command
• If there is no new SDRAM transaction, the command is Bstop issued followed by a precharge command closing the active page. • If there is an SDRAM read transaction to the same page, a new cycle begins in the next cycle. 6-34 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 225 Different examples of sequences are shown in Figure 6-7 on Read page 6-36 through Figure 6-8 on page 6-37. Table 6-14. Pin State During Read Command State MSSD high SDWE high SDCKE ADSP-TS101 TigerSHARC Processor 6-35 Hardware Reference...
Page 226 = 2 • Bus width = 64 SCLK SDCKE MSSD SDWE A11-0 QUAD-WORD QUAD-WORD DATA63-0 DQ M Figure 6-7. Bus Width = 64 (Burst Read Followed by Burst Read in the Same Page) 6-36 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 227 = 2 • Bus width = 32 SCLK SDCKE MSSD SDWE A11-0 QUAD-WO RD QUAD-WORD DATA31-0 DQ M Figure 6-8. Bus Width = 32 (Burst Read Followed by Burst Read in the Same Page) ADSP-TS101 TigerSHARC Processor 6-37 Hardware Reference...
Page 228: Write Command
• If there is no new SDRAM transaction, command is issued, Bstop followed by a precharge command closing the active page. • If there is an SDRAM write transaction to the same page, a new transaction begins on the next cycle. 6-38 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 229 Bstop issued and then, keeping to the RAS-to-precharge (t ) delay con- straint, Precharge ( ) and cycles are issued. Table 6-15. Pin State During Write Command State MSSD high SDWE high SDCKE ADSP-TS101 TigerSHARC Processor 6-39 Hardware Reference...
Page 230 For the sequence in Figure 6-10, the following is true: • latency = 2 • Bus width = 64 SCLK SDCKE MSSD SDWE A11-0 QUAD-WORD QUAD-WORD DATA63-0 Figure 6-9. Bus Width = 64 (Burst Write Followed by Burst Write in the Same Page) 6-40 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 231 = 2 • Bus width = 32 SCLK SDCKE MSSD SDWE A11-0 QUAD-WORD QUAD-WORD DATA31-0 DQ M Figure 6-10. Bus Width = 32 (Burst Write Followed by Burst Write in the Same Page) ADSP-TS101 TigerSHARC Processor 6-41 Hardware Reference...
Page 232: Refresh (Ref) Command
The purpose is to keep the SDRAM self-refreshed in case the host doesn’t interface with the SDRAM. If the host can interface with the SDRAM, it releases the SDRAM from 6-42 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 233: Programming Example
This section provides a programming example written for the Tiger- SHARC processor. The example shown in Listing 6-1 on page 6-44 demonstrates how to set up the SDRAM controller to work with the ADSP-TS101 EZ-KIT Lite™. ADSP-TS101 TigerSHARC Processor 6-43 Hardware Reference...
Page 234 SYSCON = xr0 ;; /* SDRAM setting for 32Mb DIMM module and rev 1.3 EZ-Kit */ xr0 = SDRCON_INIT | SDRCON_RAS2PC4 | SDRCON_PC2RAS3 | SDRCON_REF1200 | SDRCON_PG256 | SDRCON_CLAT2 SDRCON_ENBL ;; SDRCON = xr0 ;; 6-44 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 235 (the <–> symbol indicates “to and from”) • Internal memory <–> External memory or memory-mapped peripherals • Internal memory <–> Internal memory of another TigerSHARC processor via the cluster bus • Internal memory <–> Host processor ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 236 The TigerSHARC processor also has four external DMA request pins ) that allow for external I/O devices to request DMA services. As DMAR3–0 a response to the DMA request, the TigerSHARC processor performs DMA transfers according to DMA channel initialization. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 237 Figure 7-2 on page 7-4. In the case of a transmitter the four words contain the address of the source data, the number of words to be transferred, the address increment and the control bits. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 238 For example, it is not possible to set up a DMA with an operand length of quad-word and a modify value of two as this results in a quad-word being transmitted from a non-quad-aligned ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 239 AutoDMA registers. The X can be any value from 4 to 13 depending on whether you are writing to link port receive, transmit, or AutoDMA channels. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 240 IN DI REGISTER TRANSFER 0X80102 0X80103 SECOND NEW DMA SOURCE 0X80104 LONG POINTER ONCE MODIFIED WORD 0X80105 TRANSFER 0X80106 0X80107 (C) LONG WORD TRANSFER WITH MODIFY VALUE OF FOUR Figure 7-3. DMA Data Transfer Examples ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 241: Dma Controller Features
Receiver DMA registers are programmed with the external memory address, the address increment, the num- ber of transfers, and the control bits. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 242 • A source that can be a master on the cluster bus can write to an AutoDMA register. After data is written to the AutoDMA register, the AutoDMA channel transfers the data according to its initialization. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 243: Autodma Transfers
• Link port to external/internal memory transfers Receiver DMA registers are programmed with the exter- nal/internal memory address, the address increment, the number of transfers, and the control bits. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 244: Two-Dimensional Dma
• A two-dimensional block in memory can be transmitted via links, or a block received through links or from AutoDMA can be placed in memory as a two-dimensional array. 7-10 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 245: Chained Dma
Link and AutoDMA channels have one register each. A transmit channel has one source register. A receive link or AutoDMA channel has one desti- ADSP-TS101 TigerSHARC Processor 7-11 Hardware Reference...
Page 246: Dmar I/O Pins
DMAR2 DMAR3 FLYBY , to support DMA transfers between external peripheral devices. In IOEN Flyby transactions, internal memory or peripherals are not involved. Only channel 0 should be defined to work in Flyby mode. 7-12 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 247: Terminology
DMA transfers to and from external address space. • Transfer Control Block ( A quad-word that defines a set of parameters for the DMA operation. • DMA register A quad-word register that contains a Transfer Control Block. • chain loading ADSP-TS101 TigerSHARC Processor 7-13 Hardware Reference...
Page 248: Setting Up Dma Transfers
DMA interrupts are generated when an entire block of data has been transferred. This occurs when the DMA channel’s count register has decremented to zero and the last element of data has been transferred. 7-14 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 249: Dma Transfer Control Block Registers
128 bits long and is divided into four 32-bit registers These registers are illustrated in Figure 7-4. • Index register ( • X dimension count and increment register ( • Y dimension count and increment register ( • Control and chaining pointer ( ADSP-TS101 TigerSHARC Processor 7-15 Hardware Reference...
Page 250: Dix Register
DP REGISTER Figure 7-4. TCB Register DIx Register This is the 32-bit Index register for the DMA. It can point to the address of external, internal memory, or link ports. ADDRESS Figure 7-5. DIx Register 7-16 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 251: Dxx Register
If a two-dimensional (2D) DMA is disabled, this register is not used and any contents loaded are ignored. 16 15 Y COUNT Y MODIFY Figure 7-7. DYx Register ADSP-TS101 TigerSHARC Processor 7-17 Hardware Reference...
Page 252: Dpx Register
2DDMA Two-dimensional DMA LEN Operand length INT Interrupt enable DRQ DMA request enable CHEN Chaining enabled CHTG Chaining destination channel MS Bit 15 continued on Figure 7-9 Figure 7-8. DPx (Upper) Register Bit Descriptions 7-18 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 253 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHPT Quad-word Address (Bit 16 continued on Figure 7-8) MS Memory select for chain pointer Figure 7-9. DPx (Lower) Register Bit Descriptions ADSP-TS101 TigerSHARC Processor 7-19 Hardware Reference...
Page 254 10001 – Channel 9 Link Port 1 Receive 10010 – Channel 10 Link Port 2 Receive 10011 – Channel 11 Link Port 3 Receive 10110 – Channel 12 IFIFO AutoDMA0 Receive 10111 – Channel 13 IFIFO AutoDMA1 Receive 7-20 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 255 Thus if oper- and length is set to quad, then the address originally loaded in the register must be divisible by four. ADSP-TS101 TigerSHARC Processor 7-21 Hardware Reference...
Page 256 111 – Reserved 1 Link channel field may be programmed with any other link channel. However, CHTG CHTG should not be cross chained with any other DMA channels. 7-22 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 257: Dma Control And Status Registers
• Initializing a DMA channel to read from broadcast memory space If any of these conditions occur a hardware interrupt is generated if enabled and the status bits can only be cleared by reading from the DSTATC register. ADSP-TS101 TigerSHARC Processor 7-23 Hardware Reference...
Page 258 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved Bits17-15 continued on Figure 7-13 Figure 7-11. DSTAT (Bits 31-16) Register Bit Descriptions 7-24 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 259 111 – Address error – broadcast read. This occurs if a source TCB address field is in the range 0x1C000000 - 0x1FFFFFFF Bits17-15 continued on Figure 7-11 Figure 7-13. DSTAT (Bits 15-0) Register Bit Descriptions ADSP-TS101 TigerSHARC Processor 7-25 Hardware Reference...
Page 260: Dma Control Registers
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved PA13 PA12 Figure 7-14. DCNT (Upper) Register 7-26 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 261 PA3 Pause bit PA4 Pause bit PA5 Pause bit PA6 Pause bit PA7 Pause bit Reserved PA8 Pause bit PA9 Pause bit PA10 Pause bit PA11 Pause bit Reserved Figure 7-15. DCNT (Lower) Register ADSP-TS101 TigerSHARC Processor 7-27 Hardware Reference...
Page 262: Dcntst Register
AutoDMA register. Count (XCOUNT and YCOUNT) For EP channels, the total counts should be identical. • : when the bit is cleared DX_COUNT 2DDMA • : when the bit is set DX_COUNT * DY_COUNT 2DDMA 7-28 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 263: Type Setup – Links Transmit (Channels 4 To 7)
Type Setup – Links Receive (Channels 8 to 11) For DMA control registers, link receive channels can be set up as only one of the following: • 1 (link port), • 2 (internal memory), or • 4 (external memory) ADSP-TS101 TigerSHARC Processor 7-29 Hardware Reference...
Page 264: Type Setup – Ep (Channels 0 To 3)
In EP channels (channels 0 to 3), the bit must be the same in both registers. Alignments If the field is 2 (long-word), the following fields must be even (bit 0 cleared): • • DX_MODIFY 7-30 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 265: Address Range
When a link DMA channel (transmit or receive channel) becomes active, if the transmit buffer is empty (for transmit channel) or if the receive buffer is not empty (for receive channel), a DMA request is immediately issued. ADSP-TS101 TigerSHARC Processor 7-31 Hardware Reference...
Page 266: Dma Controller Operations
Each channel can work in handshake mode, using its pin. Either 32-bit (word), 64-bit (long-word), or 128-bit DMARx (quad-word) internal data widths can be used when transferring data between internal and external memory. 7-32 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 267: Autodma Register Control
All I/O ports (link and external) are connected to the internal memory via the three memory buses. For more information, see “Processor Microarchitecture” on page 5-3. The DMA controller gener- ates an internal memory access on one of these buses. ADSP-TS101 TigerSHARC Processor 7-33 Hardware Reference...
Page 268: Dma Channels
This must be consistent with the transfer type— field in register. (See “DPx Register” on page 7-18.) 7-34 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 269 DMA channel is to clear its DMA enable bit in the corresponding control register. Each DMA channel also has a chain pointer—the field in the CHPT register . The chain pointer is used in chained DMA operations. (See “DMA Chaining” on page 7-41.) ADSP-TS101 TigerSHARC Processor 7-35 Hardware Reference...
Page 270: Dma Channel Prioritization
The TigerSHARC processor always uses a fixed prioritization between I/O groups. Table 7-3 on page 7-38 lists the DMA groups in descending order of priority. 7-36 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 271 , channel x asserts the highest TCBx priority inside its group. If more than one channel has one of its bits set in the register , priority is resolved according to the priority list. ADSP-TS101 TigerSHARC Processor 7-37 Hardware Reference...
Page 272 Channel 6 (Link 2) ⇓ Channel 5 (Link 1) ⇓ Channel 4 (Link 0) ⇓ External Ports (EPs) ⇓ Channel 3 DMAR3 ⇓ Channel 2 DMAR2 ⇓ Channel 1 DMAR1 Channel 0 Lowest Priority DMAR0 7-38 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 273: Rotating Priority
The priority within channels 0 to 3 is kept while higher priority channels (one or more of channels 4–13) are selected. When the higher priority channel (or channels) completes its transfer, the last priority order for channels 0 to 3 is kept unchanged. ADSP-TS101 TigerSHARC Processor 7-39 Hardware Reference...
Page 274 1 wins the arbitration and continues its transfers. If there is more than one channel with priority bit set, the arbitration between these channels is in a similar round robin manner. 7-40 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 275: Dma Chaining
The DMA controller automatically reads the from internal memory and loads the values into the channel registers to set up the next DMA sequence at the end of the present one. This pro- cess is called chain loading. ADSP-TS101 TigerSHARC Processor 7-41 Hardware Reference...
Page 276: Enabling And Disabling Chaining
TCBx occurs at the end of the current block transfer. Interrupts occur at the end of the chain sequence, instead of after each transfer, when the bit is set in the last chained register. 7-42 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 277: Transfer Control Blocks And Chain Loading
TCBx • Set the (chaining enable) bit CHEN • Define the (channel target) CHTG • Define the (chaining pointer) fields, noting that the CHPT ’s address is four times the value of this field ADSP-TS101 TigerSHARC Processor 7-43 Hardware Reference...
Page 278: Chain Insertion
DX CO UNT DX MODIFY DX COUNT DY COUNT DY MODIFY DY COUNT DY MODIFY DY CO UNT DY MODIFY CHAIN POINTER CHAIN POINTER CHAI N POINTER Figure 7-16. DMA Channel 0 Chain Insertion Example 7-44 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 279: Two-Dimensional Dma
) initially contains the number of TCB DY Count words in the Y dimension (number of rows) and is decremented each time the X Count register reaches zero. When Y count reaches zero, the DMA ADSP-TS101 TigerSHARC Processor 7-45 Hardware Reference...
Page 280: Two-Dimensional Dma Operation
To disable two-dimensional DMA, the TCB DY Count 2DDMA bit must be set to zero in the register. To disable the TCB DP Control DMA channel, the field should be reset in the register. TCB DP 7-46 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 281 IN THE ROW IS 0X80104. THE NEXT ELEMENT IN THE Y DIMENSION IS THE FIRST ELEMENT IN THE NEXT ROW, 0X80108. THUS THE OFFSET VALUE IS 0X4. Figure 7-17. Two-Dimensional DMA of an 8x8 Array with Quad Operand Length ADSP-TS101 TigerSHARC Processor 7-47 Hardware Reference...
Page 282: Dma Interrupts
• The DMA channel is enabled, chaining is disabled, the DMA request bit is set, and a DMA request input transitions from high to low. • The DMA channel is enabled, chaining is disabled, and the DMA request bit is cleared. 7-48 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 283: Ending A Dma Sequence
A DMA sequence is resumed when the pause bit in one of the regis- DCNT ters is reset. (See “DCNTCL Register” on page 7-28.) Whenever the DMA request goes low again, the DMA sequence continues from where it left off. ADSP-TS101 TigerSHARC Processor 7-49 Hardware Reference...
Page 284: External Port Dma
The external address is generated according to the information in the external memory register. (See “DMA Channel Control” on page 7-15.) The internal memory address is generated according to the information in the internal memory register, where both registers 7-50 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 285: External Port Dma Transfer Types
AutoDMA data register. Writing to this address invokes the corresponding DMA channel. The configuration for the receiver in this case is described in Table 7-6 on page 7-54. ADSP-TS101 TigerSHARC Processor 7-51 Hardware Reference...
Page 286 TCBxDP Sets chaining mode CHEN 1 – Enables chaining. Defines the register to be loaded; must be the same channel. CHTG Chaining pointer – relevant when chaining is enabled. CHPT 7-52 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 287 Sets chaining mode; CHEN 1 – Enables chaining This setting must be identical to transmitter Defines register to be loaded; must be the same channel. CHTG Chaining pointer – relevant when chaining is enabled. CHPT ADSP-TS101 TigerSHARC Processor 7-53 Hardware Reference...
Page 288: Internal To External Memory
Consider the case where the transfer direction is from internal to the external memory. The configurations for transmitter and receiver s are described in Table 7-7 on page 7-55 and Table 7-8 on page 7-56 respectively. 7-54 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 289: External I/O Device To External Memory (Flyby)
Consider the case where the transfer direction is from an external I/O device to the external memory. There is no internal memory access. The configurations for transmitter and receiver s are described in Table 7-9 on page 7-57 and Table 7-10 on page 7-58 respectively. ADSP-TS101 TigerSHARC Processor 7-55 Hardware Reference...
Page 290 The setting must be identical to transmitter Defines register to be loaded; must be the same channel. CHTG Chaining pointer – relevant when chaining is enabled. CHPT For more information, see “Flyby Transactions” on page 5-34. 7-56 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 291: External Memory To External I/O Device (Flyby)
OFIFO is irrelevant. The configurations for transmitter and receiver s are described in Table 7-11 on page 7-59 and Table 7-12 on page 7-60 respectively. For more information, see “Flyby Transactions” on page 5-34. ADSP-TS101 TigerSHARC Processor 7-57 Hardware Reference...
Page 292 1 – Enables chaining. Irrelevant when the bit is set in the transmitter’s register. CHEN TCB DP Defines register to be loaded; must be channel 0. CHTG Chaining pointer – relevant when chaining is enabled. CHPT 7-58 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 293: Dma Semaphores
Since DMA channels are a system resource, a device that wants to use a DMA channel must determine whether one is currently available. It is rec- ommended this be done through software, using an agreed upon location ADSP-TS101 TigerSHARC Processor 7-59 Hardware Reference...
Page 294 0. CHTG Chaining pointer – relevant when chaining is enabled. CHPT in each processor’s memory to specify which channels are currently avail- able. This memory location should only be modified using a read-modify-write operation. 7-60 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 295: Handshake Mode
I/O device’s width. register retains the same functionality in this mode. The Tiger- DMAR0 SHARC processor outputs: addresses, memory selects, FLYBY strobes, and responds to . The external memory access behaves RD/WR ADSP-TS101 TigerSHARC Processor 7-61 Hardware Reference...
Page 296 In order to be recognized in a particular cycle, the low transition must meet the setup time specified in the data sheet, DMARx otherwise it could take effect in the following cycle. 7-62 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 297: Link Ports Dma
(one or more times depending on the packing mode). Link address is put into IFIFO with read data, whereupon the IFIFO requests an ADSP-TS101 TigerSHARC Processor 7-63 Hardware Reference...
Page 298: Receiving Link Port To Link Port
Table 7-14. Receiving Link Port to Link Port In order to move data from one link port to another link port, the receiver should be programmed as a link . See Table 7-15. 7-64 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 299 Chaining pointer – relevant when chaining is enabled. CHPT The DMA initiates a transfer by requesting the internal bus, and data is transferred from the link port that requested the DMA services to the receiver link port. ADSP-TS101 TigerSHARC Processor 7-65 Hardware Reference...
Page 300: Dma Throughput
Chaining pointer – relevant if chaining is enabled. CHPT DMA Throughput This section discusses overall DMA throughput when several DMA chan- nels are trying to access internal or external memory at the same time. 7-66 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 301: Internal Memory Dma
When data is to be transferred from internal to external memory, the internal memory data is placed in the external port’s OFIFO, completing the OFIFO write request. The external memory access then begins inde- pendently. For external-to-internal DMA, the internal bus DMA request ADSP-TS101 TigerSHARC Processor 7-67 Hardware Reference...
Page 302: Dma Operation On Boot
SHARC processor, other than the assigned DMA channel, are utilized and internal DMA throughput is not affected. DMA Operation on Boot DMA operation on booting is described in “DMA Operation on Boot” on page 10-32. 7-68 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 303 DMA occurs through the dedicated DMA channels for transmit and receive. DMA chaining is supported and all link ports can be used for booting. TigerSHARC processor link ports are not compatible with SHARC pro- cessor link ports. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 304: Link Architecture
Table 8-1 describes the I/O pins related to the link ports. There is a set of link pins for each link port. The ‘x’ in the signal name indicates the link port—0, 1, 2, or 3. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 305 , and pins. This con- LxDIR LxCLKIN LxCLKOUT LxDAT figuration might be used when differential low swing buffers are used for long twisted-wire pairs. The figure shows a set of bidirectional buffers ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 306: Transmitting And Receiving Data
LBUFTx ter when it is empty, and then transmitted. After the data is copied to the shift register, new data can be written to the register. LBUFTx ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 307 Each link port is associated with two DMA channels. One channel is used for transmitting data while the other is used for receiving data. The two DMA channels can interface with either internal or external memory. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 308 If the transmit buffer is empty (for transmit channel) or if the receive buffer is full (for receive channel), a DMA request is issued as soon as a link DMA channel (transmit or receive) becomes active. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 309: Interrupts
The link receive DMA channel is initialized to receive 256 words and write them to internal memory block 0, address 0. For more information, see “Boot Link to Internal Memory” on page 10-36. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 310: Link Port Communication Protocol
It is used when the links are buffered. The link port protocol includes a Transfer Acknowledge and an optional Connectivity Check for each quad-word transferred. Errors resulting from these handshakes are described in “Error Detection Mechanisms” on page 8-17. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 311 An example for transmit start is shown in Figure 8-4. Note LxCLKIN are shown from the transmitter’s point of view. This is also the LxCLKOUT case in the figures shown on successive pages, unless otherwise stated. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 312 When the buffer is empty, the receiver sets high (Transmit Acknowledge), to be ready LxCLKIN for another token request. 8-10 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 313 If there is more data to be transmitted, the transmitter sets the to low and waits until is driven high LxCLKOUT LxCLKIN by the receiver. ADSP-TS101 TigerSHARC Processor 8-11 Hardware Reference...
Page 314 LxCLKIN sions occur. NEXT TRANSFER NO TRAN SMI TT ER WAITS FOR NEXT TRANSFER NEXT TRANSFER ACKNOWLEDGE LXCLKIN SET ACKNOWL EDGE BEGINS LxCLKOUT LxCLKINB LxDAT7:0 Figure 8-7. Transfer Waits Because Receiver Buffer is Full 8-12 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 315 LxCLKOUT ing the former transmitter (A in this example) did not regret the token switch and can receive data. (Refer to the ADSP-TS101 TigerSHARC Embedded Processor Data Sheet.) The link has an output that indicates data direction. When...
Page 316 Figure 8-8. Token Switch from A to B A ENABLES TOKEN SWITCH A REGRETS TOKEN SWITCH A STARTS TRANSMITTING LxCLKOUT TOKEN SWITCH ENABLE ACKNOWL EDGE LxCLKIN LxDAT7:0 LxDIR (A) LxDIR (B) Figure 8-9. Transmitter Regrets a Token Switch 8-14 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 317: Transmission Delays
The former transmitter must keep the high long enough to guar- LxCLKOUT antee the token switch takes place. (See the ADSP-TS101 TigerSHARC Embedded Processor Data Sheet.) The receiver must request the token switch when it senses its is high. If the receiver does not request...
Page 318 DATA IS TRANSMI TTED BY B TIMING AT A L xCL KOUT LxCLKIN TRANSMISSION DELAY LxDAT7-0 LxDIR (A) TI MING AT B LxCLKIN LxCLKOUT LxDAT7-0 LxDIR (B) Figure 8-10. Token Switch From A to B With Delay 8-16 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 319: Error Detection Mechanisms
• The link no longer continues to transmit/receive until the error sta- tus is read (from the LSTATCx After reading the status from the destructive address, it should be reinitial- ized to start working. ADSP-TS101 TigerSHARC Processor 8-17 Hardware Reference...
Page 320: Transmitter Error Detection
The receiver compares the transmitted verification byte to the local verification byte created during data reception. If the two bytes dif- fer, the bit is set in the register and a hardware RER0 LSTATx interrupt is issued. The checksum algorithm is: 8-18 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 321: Control Register (Lctlx)
Control Register (LCTLx) The control register programs every link port and contains control bits unique to each one. There are four control registers—one for each link port. The register is read/write. ADSP-TS101 TigerSHARC Processor 8-19 Hardware Reference...
Page 322 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved Figure 8-11. LCTLx (Upper) Register Bit Descriptions 8-20 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 323 SPD Transfer Speed LTEN Transmit Enable PSIZE Packet Size TTOE Transmit Time Out check Enable CERE Connectivity Error check Enable LREN Receive/Enable RTOE Receive Time Out check Enable Reserved Figure 8-12. LCTLx (Lower) Register Bit Descriptions ADSP-TS101 TigerSHARC Processor 8-21 Hardware Reference...
Page 324 Receive/Enable LREN When disabled, any ongoing receive procedure inside the block is ceased immedi- ately and any received data is cleared. When set, the receive register is empty. Upon reset, this bit is set. 8-22 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 325: Status Register (Lstatx)
1 Both transmitter and receiver have to work at the same clock speed, although the clock doesn’t need to be fully synchronous. 2 Refer to the ADSP-TS101 TigerSHARC Embedded Processor Data Sheet for timing specifications and frequency limitations. After reset: •...
Page 326 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved Figure 8-13. LSTATx (Upper) Register Bit Descriptions 8-24 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 327 Note any error causes hardware error interrupt. Reading the Status register clears the error and resets the state machine for a new transfer. 7–6 Transmit Status 00 – Transmitter empty 01 – Transmitter partly full 11 – Transmitter full 31–8 Reserved ADSP-TS101 TigerSHARC Processor 8-25 Hardware Reference...
Page 328 Status Register (LSTATx) 8-26 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 329 The ICE, on the other hand, uses a reserved communication channel (the JTAG test access port) to control the TigerSHARC processor. This way the ICE can be non-intrusive to the system, as well as control systems that cannot communicate with a host system. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 330: Operating Modes
Debug Resources Special Instructions The TigerSHARC processor supports special instructions (traps) which are used to aid system debugging. These instructions are required to implement both software breakpoints (in debuggers) and operating system calls (for OS kernels). ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 331: Watchpoints
There are three watchpoint sets that can operate in parallel. At each watchpoint, the user can define conditions for bus access cycles and the operation the TigerSHARC processor should execute when these occur. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 332: Programming – Control And Address Pointer Registers
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 COUNTER Figure 9-1. WPxCTL (Upper) Register Bit Descriptions ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 333 R If set, read to memory transactions are monitored. W If set, write to memory transactions are monitored. EXTYPE Write SSTP/WPOR/WPAND Watchpoint register OR and AND bits Reserved Figure 9-2. WPxCTL (Lower) Register Bit Descriptions ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 334 Determines the procedure following count experiment. 00 – No exception. This option is used to get an indication of the output of the pin. 01 – Regular software exception is performed. 10 – Emulation trap is executed. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 335: Watchpoint Operation
Watchpoint Operation The following information must be programmed into the Watchpoint registers before a search can begin: • Address or address range • Master initiating the transaction • Count ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 336: Watchpoint Status (Wpistat)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reserved EX Execution Figure 9-3. WPxSTAT (Upper) Register Bit Descriptions ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 337: Instruction Address Trace Buffer (Tbuf)
Figure 9-4. WPxSTAT (Lower) Register Bit Descriptions Instruction Address Trace Buffer (TBUF) Since the program counter is not accessible in real time off chip when exe- cuting instructions from internal memory, a trace buffer has been provided to assist code debugging. ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 338: Performance Monitors
The ratio between the total count and the performance monitor counter gives the required indication. When the performance monitor counter expires, it issues an exception. 9-10 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 339: Cycle Counter (Ccnt1–0)
In this case, on a cycle where the compute block (X or Y) executes two instructions, the counter is incre- mented by two, and on bus transactions (Bits14–12) the counter could be incremented by three. ADSP-TS101 TigerSHARC Processor 9-11 Hardware Reference...
Page 340: Performance Monitor Counter
The TigerSHARC processor supports the IEEE Standard 1149.1 Test Access Port. Pins Table 9-4 describes those TigerSHARC processor pins used by JTAG emulation hardware. Underlined or overbarred pin names indicate nega- tive true signals. 9-12 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 341 A serial data output of the boundary scan path. Input Test Mode Select (JTAG) Controls the test state machine. This signal has a 100 KΩ internal pull-up resistor. Output Emulation Connected to the ADSP-TS101 DSP EZ-ICE target board connector only. ADSP-TS101 TigerSHARC Processor 9-13 Hardware Reference...
Page 342: Jtag Instruction Register
TAP state is changed to , the particular data going in and out of SHIFT-DR the TigerSHARC processor depends on the definition of the Data register selected. See the IEEE 1149.1 specification for more details. 9-14 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 343 00100 Scan register EMUCTL EMUCTL 01100 Scan register EMUSTAT EMUSTAT 11111 Bypass BYPASS When registers are scanned out of the device, the LSB is the first bit to go out of the TigerSHARC processor. ADSP-TS101 TigerSHARC Processor 9-15 Hardware Reference...
Page 344 In this case the last slots have to be filled with “no operation” (NOP) instructions. Except for the restriction of not crossing the quad-word boundary, this is similar to the assembler coding described in “Instruction Set” in the ADSP-TS101 TigerSHARC Processor Programming Reference. 9-16 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 345 . When the EMUDAT emulator executes a series of memory accesses, the TigerSHARC processor should insert hold cycles to allow all of the accesses to complete (just as it does normally). ADSP-TS101 TigerSHARC Processor 9-17 Hardware Reference...
Page 346 JTAG Functionality 9-18 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 347: Overview
• ADSP-TS101 TigerSHARC Processor Programming Reference • ADSP-TS101 TigerSHARC Embedded Processor Data Sheet Included in both the Analog Devices manuals and data sheet are references of source materials, such as Engineer-to-Engineer Notes or Application Notes, available on the Analog Devices Web site http://www.analog.com.
Page 348 See “Clock Domain” in ADSP-TS101 TigerSHARC Embedded Pro- cessor Data Sheet. High Frequency Design see the Technical article ADSP-TS101S MP System Simulation and Analysis which can be found on the Analog Devices Web site http://www.analog.com. 10-2 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 349: Tigersharc Processor Pins
SDCKE ADDR SDA10 BR7–1 FLYBY DATA IOEN LXDAT7–0 LINK BOFF DMA DEVICE DEVICES LXCLKIN DMAR3–0 (OPTIONAL) (4 MAX) LXCLKOUT DATA (OPTIONAL) LXDIR TMR0E BUSLOCK CONTROLIMP2–0 DS2–0 RESET JTAG Figure 10-1. Basic TigerSHARC Processor System ADSP-TS101 TigerSHARC Processor 10-3 Hardware Reference...
Page 350: Pin Definitions
• P = Power supply Table 10-2 includes only a brief description of pins. For a complete description, refer to the ADSP-TS101 TigerSHARC Embedded Pro- cessor Data Sheet which contains the most current and detailed information about this TigerSHARC processor product.
Page 351 DMA Request Pins Digital Drive Strength Selection DS2–0 O (o/d) Emulation I/O/A FLAG pins FLAG3–0 Flyby Mode FLYBY I/O/T Host Bus Grant Host Bus Request High Word SDRAM Data Mask HDQM Multiprocessor ID ID2–0 ADSP-TS101 TigerSHARC Processor 10-5 Hardware Reference...
Page 352 Memory Read Reset RESET System Clock Reference SCLK_N System Clock Input SCLK_P SCLK Frequency SCLKFREQ SDRAM Address bit 10 pin SDA10 I/O/T SDRAM Clock Enable SDCKE I/O/T SDRAM Write Enable SDWE Test Clock (JTAG) 10-6 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 353: Strap Pin Function Descriptions
Strap Pin Function Descriptions Some pins have alternate functions at reset. Strap options set Tiger- SHARC processor operating modes. During reset, the TigerSHARC processor samples the strap option pins. Strap pins have an approximately ADSP-TS101 TigerSHARC Processor 10-7 Hardware Reference...
Page 354: Pin Usage
0 =Required setting during reset 1 = Reserved Pin Usage This section suggests recommended handling of unused pins. If an appli- cation does not make use of a function, the associated signals (pins) may still require a connection. 10-8 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 355 (internal pull-up) SDCKE nc (internal pull-up) nc = no connection through 10k Ω resistor is required pu = pull-up to V DD_IO through 10k Ω resistor is required pd = pull-down to V ADSP-TS101 TigerSHARC Processor 10-9 Hardware Reference...
Page 356: Pin States At Reset
2 For strap pins refer to Table 10-3 on page 10-8. 3 Must be pulsed or held low after power up. For more information see the EE-68 Application Note “Analog Devices JTAG Emulation Technical Reference (2.4)” Pin States At Reset The TigerSHARC processor three-states all outputs during reset, allowing these pins to get to their internal pull-up or pull-down state.
Page 357: Power, Reset, And Clock Input Considerations
Power, Reset, and Clock Input Considerations Power Supply Sequencing For information on power supply sequencing, see “Power Supplies” in the ADSP-TS101 TigerSHARC Embedded Processor Data Sheet. Reset For information on reset, see “Reset and Booting” in the ADSP-TS101 TigerSHARC Embedded Processor Data Sheet.
Page 358: Timer Interrupt And Flag I/O Examples
Once a flag pin has been set as an output pin, the signal can be driven high or low by the TigerSHARC processor by setting or clearing Bits27– 24 of the register. The following code sample shows how to drive SQCTL signal high. FLAG2 10-12 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 359 The following sample code shows how to set up a high priority Timer0 interrupt. The interrupt service routine contains a flag toggle routine that toggles a programmable flag pin connected to a LED on the ADSP-TS101 ADSP-TS101 TigerSHARC Processor 10-13 Hardware Reference...
Page 360 /*Sit in IDLE until timer0 interrupt is generated*/ jump wait;; timer_isr_routine: /* Timer0 interrupt service routine*/ xr0 = SQCTL;; /*Read the Sequence Control Register*/ xr0 = btgl r0 by SQCTL_FLAG2_OUT_P;; /* Toggle the value of Flag 2 pin (bit 26)*/ 10-14 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 361: Clock Description And Jitter
PCB layer closest to the ground plane to keep delays stable and crosstalk low. More than one device may be at the end of the line, but the wire length between them must be short. The ADSP-TS101 TigerSHARC Processor 10-15 Hardware Reference...
Page 362: General High Speed Clock Distribution Issues
A SEPARATE BUFFER AND TRANSMISSION LINE IS NEEDED FOR EACH PROCESSOR. Figure 10-3. System Clock Distribution General High Speed Clock Distribution Issues For additional information on handling jitter, refer to ADSP-TS101 Tig- erSHARC Embedded Processor Data Sheet. 10-16 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 363: Reset And Boot
(2, 3, 4, 5, or 6) should be used for , and the same LCLKRAT source should be used for pins. Refer to the LCLK SCLK ADSP-TS101 TigerSHARC Embedded Processor Data Sheet for the AC specifications. ADSP-TS101 TigerSHARC Processor 10-17 Hardware Reference...
Page 364: Booting
TigerSHARC processor’s internal mem- ory and optional external system memory are to be initialized. The boot loader kernel source code supplied with Analog Devices software tools may be modified. For details on the boot loader kernels refer to the Engineer-to-Engineer Note EE-174: ADSP-TS101 Boot Loader Kernels Operation.
Page 365: Handling Bms
Regardless of which boot mode (master or slave) is used, each shares a common boot process. 1. The pin determines the booting method. Each DMA channel from which the TigerSHARC processor can boot is automatically configured for a 256-word (32-bit normal word) transfer. ADSP-TS101 TigerSHARC Processor 10-19 Hardware Reference...
Page 366: No Boot Mode
The DMA channel 0 interrupt vector is initialized to internal memory address 0x0. An interrupt occurs at the completion of the DMA channel 0 transfer and the TigerSHARC processor starts executing the boot loader kernel at internal memory location 0x0. 10-20 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 367 Access to memory space is only allowed via DMA; core accesses are not possible. For more information, see “Boot EPROM to Internal Memory” on page 10-33 and “EPROM Interface” on page 5-31. ADSP-TS101 TigerSHARC Processor 10-21 Hardware Reference...
Page 368: Host Boot
Booting Analog Devices supplies a default EPROM boot loader kernel TS101_prom.asm ADDRESS 8-BIT EPROM A23-0 A23-0 D7-0 D1-0 ADSP-TS101 8-BIT DATA Figure 10-4. PROM Booting Host Boot Booting the TigerSHARC processor from a 32-bit or 64-bit host processor is performed via the data and address buses of the external port.
Page 369 “TigerSHARC processor Pipelined Interface” on page 6-14 for details on the pipelined protocol. The host boot loader kernel provided by Analog Devices with the Visu- alDSP++ software development tools assumes the processor has been configured for normal-word transfers. Upon reset, the default state of AutoDMA is configured for quad-word accesses.
Page 370: Link Port Boot
AUTODMA to accept normal word transfers prior to initiating the booting process. For complete details on the patch and operation of the boot loader kernels provided by Analog Devices, refer to the Engineer-to-Engineer Note EE-174: ADSP-TS101 Boot Loader Kernels Operation. Link Port Boot This section describes how booting from a link port is performed.
Page 371 TS101_link.asm alDSP++ software development tools. The default link port loader kernel provided by Analog Devices within the VisualDSP++ software development tools uses link port #3 to perform link port booting. If another link port is required for booting the Tiger-...
Page 372: Booting A Multiprocessor System
DSPs that program execution can begin when it has finished booting. Note that the other DSPs may be in an idle state at the time that the last TigerSHARC processor informs them that it has completed booting. 10-26 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 373 DSPs can boot either identical code or different code from the EPROM. If the processors load different code, a jump table (based on processor ID) can be used to select the code for each processor. ADSP-TS101 TigerSHARC Processor 10-27 Hardware Reference...
Page 374: A Single Tigersharc Processor Boots Other Processors
EPROM. All other pro- ID2–0 cessors should have their signals connected to V through a pull- DD_IO -up resistor, which configures them for host booting. Leaving all the other 10-28 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 375 An example system that uses this “one-boots-others” technique appears in Figure 10-6. ADDR ADDR31-0 ADDR23-0 DATA63-0 DATA DATA7-0 ADSP-TS101 VDDIO 8-BIT (S0) EPROM ADDR31-0 DATA63-0 ADSP-TS101 (S1) VDDIO ADDR31-0 DATA63-0 ADSP-TS101 (S7) Figure 10-6. Sequential Booting from an EPROM ADSP-TS101 TigerSHARC Processor 10-29 Hardware Reference...
Page 376: Multiprocessor Host Booting
(Recall: Writes to the broadcast region access the internal memory of all processors in the multiprocessing system. For more information on MMS space and broadcast writes, “Internal Memory Access” on page 2-7). 10-30 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 377: Memory Initialization During Boot
Linker Description File (LDF) to direct the linker to omit an output sec- tion from the output file. For details on LDF and , see the SHT_NOBITS VisualDSP++ Linker and Utilities Manual for TigerSHARC DSPs. ADSP-TS101 TigerSHARC Processor 10-31 Hardware Reference...
Page 378: Multiprocessor Link Port Booting
DMA, by default, moves only 256 words to internal memory (locations 0x00000000-0x000000ff) that comprise the boot loader (supplied with TigerSHARC processor tools). The boot loader, in turn, loads the remaining user code. 10-32 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 379: Boot Eprom To Internal Memory
“Internal Memory” in the TCB DP receiver’s register. Configuration information for the regis- TCB DP TCB DP ter is detailed in Table 10-5 on page 10-34 and Table 10-6 on page 10-35. ADSP-TS101 TigerSHARC Processor 10-33 Hardware Reference...
Page 380: Eprom Tcb
Table 10-5. EPROM Boot – EPROM TCB Transmitter TCB Configuration Register Field Description 0x00000000 Number of words to transfer is 256. Address modifier is set to 0x0004. 0x00000000 Boot EPROM 2DDMA Word CHEN CHTG 0x00000 CHPT 10-34 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 381: Internal Memory Tcb
Table 10-6. EPROM Boot – Internal Memory TCB Receiver TCB Configuration Register Field Description 0x00000000 Number of words to transfer is 256. Address modifier is set to 0x0001. 0x0000 Internal memory 2DDMA Word CHEN CHTG 0x00000 CHPT ADSP-TS101 TigerSHARC Processor 10-35 Hardware Reference...
Page 382: Boot Link To Internal Memory
Table 10-7. Link Boot – Internal Memory TCB Receiver TCB Configuration Register Field Description 0x00000000 Number of words to transfer is 256. Address modifier is set to 0x0004. 0x0000 Internal memory 2DDMA Quad-word CHEN CHTG 0x00000 CHPT 10-36 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 383: Boot Autodma Register To Internal Memory
Table 10-8. DMA Data Register Boot – Internal Memory TCB Receiver TCB Configuration Register Field Description 0x00000000 Number of words to transfer is 256. Address modifier is set to 0x0004. 0x0000 Internal memory 2DDMA Quad CHEN CHTG 0x00000 CHPT ADSP-TS101 TigerSHARC Processor 10-37 Hardware Reference...
Page 384: Jtag Issues
JTAG Issues JTAG Issues The Analog Devices family of emulators are tools which aid developers when testing and debugging a hardware and software system. Analog Devices has supplied an IEEE 1149.1 compliant Joint Test Action Group (JTAG) Test Access Port (TAP) on each JTAG TigerSHARC processor.
Page 385: Signal Integrity
It is recommended that users perform simulation tests to ensure proper signal integrity. For these purposes, Analog Devices supplies IBIS models. TigerSHARC processor IBIS models are available on the Analog Devices Web site http://www.analog.com.
Page 386: Adsp-Ts101 Processor Ez-Kit Lite
Topics covered in the book include: • High-Speed Properties of Logic Gates • Measurement Techniques • Transmission Lines • Ground Planes and Layer Stacking 10-40 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 387 • Terminations • Vias • Power Systems • Connectors • Ribbon Cables • Clock Distribution • Clock Oscillators High-Speed Digital Design: A Handbook of Black Magic, Johnson and Gra- ham, Prentice Hall, Inc., ISBN 0-13-395724-1. ADSP-TS101 TigerSHARC Processor 10-41 Hardware Reference...
Page 388 Resources and References 10-42 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 389 All DSPs Boot In Turn From A tions registers Single EPROM 10-26 Activ (Activate command) 6-35 ALU Registers 2-13 Activ-to-Pre delay (tRAS) 6-2 ALU registers 2-13 Additional Literature -xxii Analog Devices products -xxiii Additional Reference Material arbitration 1-16 10-2 architecture Address Bus (ADDR) 2-2, 5-1,...
Page 390 EPROM boot (BMS) 3-1, 4-2, 6-35, 6-38, 6-39 5-5, 10-8, 10-32–10-34 Burst (BRST) 5-5, 5-16, 5-18, 5-50 link boot 3-1, 4-2, 8-7 bus 1-16 no boot 3-1 bus arbitration 1-20, 5-1, 5-3, 5-5, Boot AutoDMA Register to Inter- ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 391 2-11–2-12 5-48 compute block status registers BUSLOCK pin see bus lock 2-13 merged access 2-11 multiplier registers 2-13 shifter registers 2-13 CAS Before RAS 6-42 unmapped compute block reg- see also SDRAM isters 2-12 refresh ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 392 4-2, 4-8, 5-2, 5-3, 5-7, 5-9, 5-10, data alignment buffer 1-17 5-31, 5-34–5-37, 7-1, 8-5 accesses 1-17 AutoDMA 2-44, 4-8, 7-8, Data Alignment Buffer (DAB) 7-10, 7-12, 7-14, 7-15, 4-10 7-28, 7-30, 7-33, 7-34, Data Bus (DATA) 5-1, 5-4, 5-31, ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 393 7-60, 7-64, 7-65, 7-66, DMA controller 1-22, 7-7– 10-34, 10-35, 10-36, 7-10, 7-32–7-49, 10-32 10-37 DMA interrupt 2-20–2-21, 4-2, DMA Architecture Overview 7-11 4-5–4-6, 7-48 DMA Chaining 7-41 DMA memory access 7-34– DMA Channel Control 7-15 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 394 Emulation and Test Support 1-24 DMA Semaphores 7-59 Emulation Debug 4-10 DMA Status Register (DSTAT) emulation debug 4-10 7-23 Emulation Mode 3-3 DMA Throughput 7-66 emulation mode 3-1, 3-2, 3-3–3-4, DMA Transfer Control Block Reg- 4-10, 4-16, 9-2 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 395 External Memory 1-19 Flag Pins 3-8 external memory 1-19, 1-21, 1-22, Flash memory interface 5-3, 5-33 2-2, 2-4–2-5, 5-3, 5-9, 7-54, 7-67 Flyby (FLYBY) 5-3, 5-5, 5-34– External Memory Bank Space 2-4 5-37, 7-8, 7-55–7-57 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 396 Host Bus Grant (HBG) 1-21, 5-38, Instruction Address Trace Buffer 5-40, 5-43, 5-47, 5-51 (TBUF) 9-9 Host Bus Request (HBR) 1-21, instruction dispatch/decode, See 5-38, 5-40, 5-41, 5-43, 5-46 sequencer Host Interface 1-21, 5-48 viii ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 397 4-16, 4-23–4-25 Internal Memory TCB 10-35 IVSW (Software Interrupt Internal Memory TCB 7-53, 7-55 Vector register) Internal Memory TCB 7-54 4-9, 4-23 Internal to External Memory 7-54 vector 1-21, 2-20, 2-21, 4-6, Internal Transfer 1-17 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 398 Interrupts 4-1, 8-7 code 9-15 interrupts timers 4-4 Interrupts Generated by On-Chip L unit, See ALU Modules 4-4 LCLK (Local Clock) 3-1, 5-47 Introduction 1-1 LCLKRAT (Local Clock Multipli- IRQ (Interrupt Request) 2-19, er) 3-2 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 399 LCLK 8-4–8-6 Low Power Mode 3-6 Link Port Boot 10-24 low power mode 3-6 link port boot 10-24 Low Word SDRAM Data Mask Link Port Communication Proto- (LDQM) 6-7, 6-9 col 8-8 low-power mode 3-8 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 400 Multiprocessor ID (ID) 2-2, 2-5, mode 3-1, 3-2–3-5, 9-2 5-7, 5-9 emulation mode 3-1, 3-2, 3-3– Multiprocessor Link Port Booting 3-4, 4-10, 4-16, 9-2 10-32 supervisor mode 3-1, 3-2, 3-4, Multiprocessor Space 2-5 user mode 3-1, 3-2, 3-5, 9-2 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 401 Performance Monitor Mask – PMASK see register PRFM 2-23, 9-11 post-modify addressing 1-12 Performance Monitors 9-10 post-modify operator 1-12 Pin Definitions 10-4 Power Supply Sequencing 10-11 Pin State During ACT Command Power, Reset and Clock Input 6-33 ADSP-TS101 TigerSHARC Processor xiii Hardware Reference...
Page 402 (bus lock) 2-38, dress Pointer Registers 9-4 2-41, 3-7, 5-47, 5-48 Purpose of This Manual -xix compute block status registers purpose of this manual -xix 2-13 DMA registers 2-41, 7-15– 7-31 quad access 1-17 EMUIR register 4-23 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 403 2-13 PMASK registers 2-17, 2-19, unmapped compute block reg- 3-4, 4-11, 4-13–4-14, isters 2-12 4-15, 4-16, 4-18, 4-19, Ureg (Universal Register) 4-22, 4-23, 4-25 1-21, 2-6, 2-7, 2-9, register groups 2-9–2-47 2-12, 2-14, 2-15, 2-29, ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 404 Rotating Priority 7-39 link registers 2-10, 2-47 Row Address Strobe (RAS) 5-1, sequencer registers 2-10 6-7, 6-9 Register J31 RTI instruction (Return from Inter- JSTAT 2-15 rupt) 4-13, 4-15, 4-19, 4-22–4-23, Register K31 4-24, 4-25 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 405 SDRAM programming 6-43 (Page Boundary) – Bits5-4 6-25 SDRAM protocol 2-4, 5-1, Self-Refresh (SREF) Command 5-34 6-42 SDRAM Write Enable (SD- semaphores 1-20, 5-47, 5-51, 7-59 WE) 6-8, 6-9, 6-34 sequencer 1-13 SDRAM Control Register ADSP-TS101 TigerSHARC Processor xvii Hardware Reference...
Page 406 0x180480) 2-34 Slow Device Protocol 5-14, 5-27 SYSCON System Configuration slow device protocol 5-2, 5-3, Register 2-34, 2-41, 5-2, 5-11– 5-14, 5-27–5-30, 5-34, 5-51 5-15, 5-17, 5-22, 5-27, 5-30, 5-48, xviii ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 407 Registers 7-15 test access port (TAP) 10-38 Transfer Control Blocks and Chain Test Access Port (TAP) controller Loading 7-43 9-14 Transmission Delays 8-15 Test Clock (TCK) 9-13 Transmitter Error Detection 8-18 Test Data Input (TDI) 9-13 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 408 Watchpoint Control – WP0CTL, Understanding DQM Operation WP1CTL and WP2CTL 2-25 6-29 Watchpoint Operation 9-7 Unmapped Compute Block Regis- Watchpoint Status – WP0STAT, ters 2-12 WP1STAT and WP2STAT 2-27 Ureg (Universal Register) Watchpoint Status (WPiSTAT) ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 409 Width 6-14, 6-17 Write Command 6-38 Word Page Size 256, 64-Bit Bus Write High (WRH) 5-4, 5-16, Width 6-13 5-18, 5-27 Word page Size 512, 32-Bit Bus Write Low (WRL) 5-4, 5-16, 5-18, Width 6-15 5-27 ADSP-TS101 TigerSHARC Processor Hardware Reference...
Page 410 INDEX xxii ADSP-TS101 TigerSHARC Processor Hardware Reference...

Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

Preface

Introduction

Memory and Register Map

Core Controls

Cluster Bus

Sdram Interface

Direct Memory Access

Link Ports

Interrupts

Debug Functionality

System Design

Quick Links

Related Manuals for Analog Devices ADSP-TS101 TigerSHARC

Summary of Contents for Analog Devices ADSP-TS101 TigerSHARC