Arithmetic Logic Unit (Alu) - Analog Devices ADSP-TS101 TigerSHARC Hardware Reference Manual

quad parallel operations on quad-aligned data allow fast processing
of array data. Byte operations are also supported for octal-aligned
data.
• Floating-point format
These include 32-bit normal word and 40-bit extended word.
Floating-point operations are single or extended precision. The
normal word floating-point format is the standard IEEE format,
and the 40-bit extended-precision format occupies a double word
(64 bits) with eight additional LSBs of mantissa for greater
accuracy.
Each compute block has a general-purpose, multi-port, 32-word data reg-
ister file for transferring data between the computation units and the data
buses and storing intermediate results. All of these registers can be
accessed as single-, dual-, or quad-aligned registers. For more information
on the register file, see "Compute Block Register Files" on page 2-10.

Arithmetic Logic Unit (ALU)

The ALU performs arithmetic operations on fixed-point and floating-
point data and logical operations on fixed-point data. The source and des-
tination of most ALU operations is the compute block register file.
On the TigerSHARC processor, the ALU includes a special sub-block,
which is referred to as the communications logic unit (CLU). The CLU
instructions are designed to support different algorithms used for commu-
nications applications. The algorithms that are supported by the CLU
instructions are:
• Viterbi Decoding
• Turbo-code Decoding
• De-spreading for code-division-multiple-access (CDMA) systems
ADSP-TS101 TigerSHARC Processor
Hardware Reference
Introduction
1-9