External Bus Interface Unit - Analog Devices ADSP-BF537 EZ-KIT Lite Manual

The core voltage and the core clock rate can be set on the fly by the pro-
cessor. The input clock is 25 MHz. A 32.768 kHz crystal supplies the
real-time clock (RTC) inputs of the processor. The default boot mode for
the processor is flash boot. See
page 2-13 for information about changing the default boot mode.

External Bus Interface Unit

The external bus interface unit (EBIU) connects external memory to the
ADSP-BF537 processor. The unit includes a 16-bit wide data bus, an
address bus, and a control bus. On the EZ-KIT Lite, the EBIU connects
to the SDRAM, flash, and expansion interfaces.
The 64M bytes (32M x 16 bits) of SDRAM connect to the synchronous
memory select 0 pin (
for information about configuring the SDRAM. Note that SDRAM clock
is the processor's clock out (
The flash memory device connects to the asynchronous memory select sig-
nals, through
AMS3
memory. The processor can use this memory for both booting and storing
information during normal operation. Refer to
page 1-15 for details.
All of the address, data, and control signals are available externally via the
expansion interface (
in "ADSP-BF537 EZ-KIT Lite Schematic" on page
ADSP-BF537 EZ-KIT Lite Evaluation System Manual
ADSP-BF537 EZ-KIT Lite Hardware Reference
"Boot Mode Select Switch (SW16)" on
). Refer to
SMS0
), which must not exceed 133 MHz.
CLK OUT
. The device provides a total of 4M bytes of flash
AMS0
). The pinout of these connectors can be found
J1–3
"SDRAM Interface" on page 1-13
"Flash Memory" on
B-1.
2-3