Operating Modes; Window Processing; 40-Bit Floating-Point Mode - Analog Devices SHARC ADSP-214 Series Hardware Reference Manual

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For N biquad stages, the order of coefficients should be as follows:

b01, b11, –a11, b21, –a21, dk21, dk11,

b02, b12, –a12, b22, –a22, dk22, dk12

b0N, b1N, –a1N, b2N, –a2N, dk2N, dk1N.

where bxN and axN are the coefficients ([b, a]) for the Nth biquad

Operating Modes

The accelerator can be operated in the following modes.

Sample based processing mode is selected by configuring window size to 1.

In this mode, one sample from a particular channel is processed through

all the biquads of that channel and the final output sample is calculated.

In window based mode, multiple output samples (up to 1024) equal to the

window size of that channel are calculated. After these calculations are

complete, the accelerator begins processing the next channel. A configu-

rable window size parameter is provided to specify the length of the

In 40-bit floating-point mode, the input data/coefficient is treated as a

40-bit floating-point number. 40-bit floating-point MAC operations gen-

erate 40-bit results. This mode can be selected by setting bit 12 of the

Since the DMA bus width is only 32 bits, in 40-bit mode the IIR acceler-

ator performs two packed 32-bit accesses to the memory to fetch one

40-bit input or coefficient data, or to store one 40-bit output word. The

ADSP-214xx SHARC Processor Hardware Reference

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