Buses; On-Chip Peripherals; Serial Ports - Analog Devices adsp-2100 Manual

1 Introduction
1.2.3

Buses

The processors have five internal buses. The program memory address
(PMA) and data memory address (DMA) buses are used internally for the
addresses associated with program and data memory. The program
memory data (PMD) and data memory data (DMD) buses are used for the
data associated with the memory spaces. The buses are multiplexed into a
single external address bus and a single external data bus; the
and
PMS
intermediate results directly between the various computational units.
The PMA bus is 14 bits wide allowing direct access of up to 16K words of
mixed instruction code and data. The PMD bus is 24 bits wide to
accommodate the 24-bit instruction width.
The DMA bus is 14 bits wide allowing direct access of up to 16 K words of
data. The data memory data (DMD) bus is 16 bits wide. The DMD bus
provides a path for the contents of any register in the processor to be
transferred to any other register or to any data memory location in a single
cycle. The data memory address comes from two sources: an absolute
value specified in the instruction code (direct addressing) or the output of
a data address generator (indirect addressing). Only indirect addressing is
supported for data fetches from program memory.
The program memory data (PMD) bus can also be used to transfer data to
and from the computational units through direct paths or via the PMD-
DMD bus exchange unit. The PMD-DMD bus exchange unit permits data
to be passed from one bus to the other. It contains hardware to overcome
the 8-bit width discrepancy between the two buses, when necessary.
1.3

ON-CHIP PERIPHERALS

This section describes the additional functional units which are included
in various processors of the ADSP-2100 family.
1.3.1

Serial Ports

Most ADSP-21xx processors have two bidirectional, double-buffered serial
ports (SPORTs) for serial communications. The SPORTs are synchronous
and use framing signals to control data flow. Each SPORT can generate its
serial clock internally or use an external clock. The framing sync signals
may be generated internally or by an external device. Word lengths may
vary from three to sixteen bits. One serial port, SPORT0, has a
multichannel capability that allows the receiving or transmitting of
arbitrary data words from a 24-word or 32-word bitstream. The other
1 – 8
signals select the different address spaces. The R bus transfers
,
BMS DMS