Changing System Clock During Runtime - Analog Devices SHARC ADSP-21368 Hardware Reference Manual

Changing System Clock During Runtime

All timing specifications are normalized to the system clock. Since most of
these are minimum specifications, (except t
ification), a variation of the system clock violates a specific specification
and causes a performance degradation for the other specifications.
The reduction of system clock violates the minimum specifications, while
increasing the system clock violates the maximum t
Therefore, careful software control is required to adapt these changes.
For most applications, the SDRAM power-up sequence and writ-
ing of the mode register needs to occur only once. Once the
power-up sequence has completed, the
again unless a change to the mode register is desired.
The recommended procedure for changing the system frequency
is as follows.
SDCLK
1. Set the SDRAM to self-refresh mode by writing a 1 to the
SDSRF
2. Poll the
3. Execute the desired PLL programming sequence. (For
details see
4. Wait until the signal
ensures that the PLL has settled to the new frequency.
5. Reprogram the SDRAM registers (
appropriate to the new
SDSRF
6. Bring the SDRAM out of self-refresh mode by performing a
read or write access.
ADSP-21368 SHARC Processor Hardware Reference
bit of register.
SDCTL
bit of
SDSRA SDSTAT
"PLL Programming Examples" on page
RESETOUT
SDCLK
bit is set.
External Port
, which is a maximum spec-
REF
specification.
REF
bit should not be set
SDPSS
register for self-refresh grant.
/ is asserted which
CLKOUT
,
SDRRC SDCTL
frequency and assure that the
14-16).
) with values
3-73