System Architecture - Analog Devices ADSP-BF561 EZ-KIT Lite Manual

System Architecture

System Architecture
This section describes the processor's configuration on the EZ-KIT Lite
board.
JTAG Header
OSC
30MHz
A5V A3.3V A1.8V
Power Regulation
Figure 2-1. System Architecture
This EZ-KIT Lite has been designed to demonstrate the capabilities of the
ADSP-BF561 Blackfin processor. The processor has an IO voltage of
3.3V. The core voltage and the core clock rate can be set on the fly by the
processor. The input clock is 30 MHz.
2-2
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SDRAM
16Mx32
JTAG PORT
ADSP-BF561
Processor
PLL
UART SPI SPORT 0
3.3V
ADM3202
AD1836
RS232
CODEC
TX/RX
Stereo In Stereo Out
RS-232
Phono
DB9 Male
Jacks (4) Jacks (6)
ADSP-BF561 EZ-KIT Lite Evaluation System Manual
FLASH
Expansion
4Mx16
Connectors (3)
EBUI
GPIO (PF)
Clock
Clock
SPORT 1 PPI1/PF PPI2/PF
To Exp
Conn
ADV7183A ADV7179
Video Video
Decoder Encoder
SPORT0
CONN
Video IN Video OUT
Phono Phono Phono
Jacks (3) Jacks (3)
ADSP-BF561
INTERFACES:
- GPIO
- PPI
- SPORT
- SPI
- etc.
MISC CONTROL:
- AD1836 Reset
- ADV7183A Reset
- ADV7179 Reset
- etc.
PPI OSC
Clock 27MHz
LEDs