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Interrupt Controller
Interrupt Controller
The DAI contains a dedicated interrupt controller that signals the core
when DAI peripheral events occur.
System versus Exception Interrupts
Generally, interrupts are classified as system or exception. Exception
events include any hardware interrupts (for example, resets) and emula-
tion interrupts, math exceptions, and illegal accesses to memory that does
not exist.
Programs can manage responses to signals by configuring registers. In a
sample audio application, for example, upon detection of a change of pro-
tocol, the output can be muted. This change of output and the resulting
behavior (causing the sound to be muted) results in an alert signal (an
interrupt) being introduced in response (if the detection of a protocol
change is a high priority interrupt).
Exception events are treated as high priority events. In comparison, system
interrupts are "deterministic"—specific events emanating from a source
(the causes), the result of which is the generation of an interrupt. The
expiration of a timer can generate an interrupt, a signal that a serial port
has received data that must be processed, a signal that an SPI has either
transmitted or received data, and other software interrupts like the inser-
tion of a trap that causes a breakpoint—all are conditions that tell the core
that an event has occurred.
Since DAI specific events generally occur infrequently, the DAI interrupt
controller classifies such interrupts as either high or low priority inter-
rupts. Within these broad categories, programs can indicate which
interrupts are high and which are classified as low.
5-24
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ADSP-2136x SHARC Processor Hardware Reference
for the ADSP-21362/3/4/5/6 Processors
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