Hip Functional Description - Analog Devices adsp-2100 Manual

7 Host Interface Port
The functions of the following pins are determined by HMD0 and HMD1
as described above:
HD15-0/HAD15-0 are either a data bus or a multiplexed address/data
bus. (Only the 3 least significant address bits are used.)
HRD/HRW is either a read strobe or a read/write select (1=read, 0=write).
HWR/HDS is either a write strobe or a data strobe.
HA2/ALE is either the most significant host address bit or an address
latch enable.
HA1-0 are either the two least significant host address bits or are unused.
7.3 HIP
FUNCTIONAL DESCRIPTION
The HIP consists of three functional blocks, shown in Figure 7.1: a host
control interface block (HCI), a block of six data registers (HDR5-0) and a
block of two status registers (HSR7-6). The HIP also includes an associated
HMASK register for masking interrupts generated by the HIP. The HCI
provides the control for reading and writing the host registers. The two
status registers provide status information to both the host and the ADSP-
21xx core.
The HIP data registers HDR5-0 are memory-mapped into internal data
memory at locations 0x3FE0 (HDR0) to 0x3FE5 (HDR5). These registers
can be thought of as a block of dual-ported memory. None of the HDRs
are dedicated to either direction; they can be read or written by either the
host or the ADSP-21xx. When the host reads an HDR register, a maskable
HIP read interrupt is generated. When the host writes an HDR, a
maskable HIP write interrupt is generated.
The read/write status of the HDRs is also stored in the HSR registers.
These status registers can be used to poll HDR status. Thus, data transfers
through the HIP can be managed by using either interrupts or a polling
scheme, described later in this chapter.
7 – 4