Functional Description - Analog Devices ADSP-21261 SHARC Hardware Reference Manual

Functional Description

• Master or slave booting from a master SPI device
• DMA capability to allow transfer of data without core overhead
Functional Description
The SPI interface contains a Transmit Shift (
( ) register. The
RXSR
ter receives data synchronously with the SPI clock signal (
Figure 10-1 shows a block diagram of the SPI interface. The data is shifted
into or out of the shift registers on two separate pins: the Master In Slave
Out ( ) pin and the Master Out Slave In (
MISO
MOSI
M S
RXSR
RX SHIFT REGISTER
RXSPI
RECEIVE
REGISTER
Figure 10-1. SPI Block Diagram
10-2
register serially transmits data and the
TXSR
MISO SPICLK
M S
SPI INTERFACE
TXSR
DM DATA BUS
PM DATA BUS
32
I/0 DATA BUS
ADSP-2126x SHARC Processor Hardware Reference
) and a Receive Shift
TXSR
) pin.
MOSI
SPIDS
FLAGX
LOGIC
TXSR
TX SHIFT REGISTER
TXSPI
TRANSMIT
REGISTER
regis-
RXSR
).
SPICLK
SPI INTERNAL
CLOCK
GENERATOR
SPISTAT
SPICTL
SPI IRQ OR
DMA REQUEST