Analog Devices AD73360L Manual
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Analog Devices AD73360L Manual

Analog Devices AD73360L Manual

Six-input channel analog front end
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FEATURES

Six 16-Bit A/D Converters
Programmable Input Sample Rate
Simultaneous Sampling
76 dB SNR
64 kS/s Maximum Sample Rate
–95 dB Crosstalk
Low Group Delay (25 s Typ per ADC Channel)
Programmable Input Gain
Flexible Serial Port Which Allows Multiple Devices to
Be Connected in Cascade
Single (2.7 V to 3.6 V) Supply Operation
80 mW Max Power Consumption at 2.7 V
On-Chip Reference
28-Lead SOIC Package
APPLICATIONS
General-Purpose Analog Input
Industrial Power Metering
Motor Control
Simultaneous Sampling Applications

GENERAL DESCRIPTION

The AD73360L is a six-input channel analog front-end proces-
sor for general-purpose applications, including industrial power
VINP1
VINN1
VINP2
VINN2
VINP3
VINN3
REFCAP
REFOUT
VINP4
VINN4
VINP5
VINN5
VINP6
VINN6
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

FUNCTIONAL BLOCK DIAGRAM

SIGNAL
0/38dB
CONDITIONING
PGA
SIGNAL
0/38dB
CONDITIONING
PGA
SIGNAL
0/38dB
CONDITIONING
PGA
REFERENCE
SIGNAL
0/38dB
CONDITIONING
PGA
SIGNAL
0/38dB
CONDITIONING
PGA
SIGNAL
0/38dB
CONDITIONING
PGA
metering or multichannel analog inputs. It features six 16-bit
A/D conversion channels, each of which provides 76 dB signal-
to-noise ratio over a dc-to-4 kHz signal bandwidth. Each
channel also features a programmable input gain amplifier (PGA)
with gain settings in eight stages from 0 dB to 38 dB.
The AD73360L is particularly suitable for industrial power
metering as each channel samples synchronously, ensuring that
there is no (phase) delay between the conversions. The AD73360L
also features low group delay conversions on all channels.
An on-chip reference voltage is included with a nominal value
of 1.2 V.
The sampling rate of the device is programmable, with four
separate settings offering 64 kHz, 32 kHz, 16 kHz, and 8 kHz
sampling rates (from a master clock of 16.384 MHz).
A serial port (SPORT) allows easy interfacing of single or cas-
caded devices to industry-standard DSP engines. The SPORT
transfer rate is programmable to allow interfacing to both fast
and slow DSP engines.
The AD73360L is available in 28-lead SOIC package.
ANALOG
DECIMATOR
-
MODULATOR
ANALOG
-
DECIMATOR
MODULATOR
ANALOG
-
DECIMATOR
MODULATOR
AD73360L
ANALOG
-
DECIMATOR
MODULATOR
ANALOG
DECIMATOR
-
MODULATOR
ANALOG
-
DECIMATOR
MODULATOR
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
Six-Input Channel
Analog Front End
AD73360L
SDI
SDIFS
SCLK
RESET
SERIAL
I/O
MCLK
PORT
SE
SDO
SDOFS
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000

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Summary of Contents for Analog Devices AD73360L

  • Page 1: Features

    –95 dB Crosstalk metering as each channel samples synchronously, ensuring that Low Group Delay (25 s Typ per ADC Channel) there is no (phase) delay between the conversions. The AD73360L Programmable Input Gain also features low group delay conversions on all channels.
  • Page 2 (AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 3.6 V; DGND = AGND = 0 V, f = 16.384 MHz, AD73360L–SPECIFICATIONS MCLK = 8.192 MHz, f = 8 kHz; T to T , unless otherwise noted.)

  • Page 3: Specifications

    AD73360L AD73360LA Parameter Unit Test Conditions/Comments LOGIC OUTPUT |IOUT| ≤ 100 µA , Output High Voltage – 0.4 |IOUT| ≤ 100 µA , Output Low Voltage µA Three-State Leakage Current –10 POWER SUPPLIES AVDD1, AVDD2 DVDD See Table I NOTES Operating temperature range is as follows: –40°C to +85°C.

  • Page 4: Timing Diagrams

    AD73360L Figure 1. MCLK Timing 100 A TO OUTPUT 2.1V –10 –85 –75 –65 –55 –45 –35 –25 –15 –5 15pF 3.17 – dBm0 100 A Figure 5. S/(N+D) vs. V (ADC @ 3 V) Over Voiceband Bandwidth (300 Hz–3.4 kHz) Figure 2.

  • Page 5: Absolute Maximum Ratings

    WARNING! accumulate on the human body and test equipment and can discharge without detection. Although the AD73360L features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are ESD SENSITIVE DEVICE recommended to avoid performance degradation or loss of functionality.

  • Page 6: Pin Function Descriptions

    SCLK and is ignored when SE is low. Serial Data Input of the AD73360L. Both data and control information may be input on this pin and are clocked on the negative edge of SCLK. SDI is ignored when SE is low.

  • Page 7: Terminology

    0 dBm0 for each ADC. The absolute gain specification an alphabetic character (A–E). There are eight is used for gain tracking error specification. read/write control registers on the AD73360L— Crosstalk designated CRA through CRE. Crosstalk is due to coupling of signals from a given channel to...

  • Page 8: Functional Description

    A/D converter and decimator sections. Each of these sections is sampling, where the sampling rate is many times the highest described in further detail below. frequency of interest. In the case of the AD73360L, the initial sampling rate of the sigma-delta modulator is DMCLK/8. The Encoder Channel...

  • Page 9: Decimation Filter

    Figure 7 shows the various stages of filtering that are employed Decimation Filter in a typical AD73360L application. In Figure 7a we see the trans- The digital filter used in the AD73360L carries out two impor- fer function of the external analog antialias filter. Even though it tant functions.

  • Page 10: Voltage Reference

    In this mode, control information can be written to or external circuitry by setting the RU bit (CRC:6) of CRC. read from the AD73360L. In Data Mode (CRA:0 = 1), any infor- mation that is sent to the device is ignored, while the encoder Serial Port (SPORT) section (ADC) data is read from the device.

  • Page 11: Control Register Tables

    Bits 10–8 Register Address This 3-bit field is used to select one of the eight control registers on the AD73360L. Bits 7–0 Register Data This 8-bit field holds the data that is to be written to the selected register provided the device address field is zero.
  • Page 12 AD73360L Table VI. Control Register B Description CONTROL REGISTER B C E E MCD2 MCD1 MCD0 SCD1 SCD0 Bit Name Description Decimation Rate (Bit 0) Decimation Rate (Bit 1) SCD0 Serial Clock Divider (Bit 0) SCD1 Serial Clock Divider (Bit 1)
  • Page 13 AD73360L Table IX. Control Register E Description CONTROL REGISTER E PUI4 I4GS2 I4GS1 I4GS0 PUI3 I3GS2 I3GS1 I3GS0 Bit Name Description I3GS0 ADC3:Input Gain Select (Bit 0) I3GS1 ADC3:Input Gain Select (Bit 1) I3GS2 ADC3:Input Gain Select (Bit 2) PUI3 Power Control (ADC3);...

  • Page 14: Register Bit Descriptions

    CRA:0 Data/Program Mode. This bit controls the operating mode of the AD73360L. If CRA:1 is 0, a 0 in this bit places the part in Program Mode. If CRA:1 is 0, a 1 in this bit places the part in Data Mode.

  • Page 15: Sport Register Maps

    (CRH:0–5) is set to 1. Setting this bit to 0 will select Noninverted (Normal) Mode for all channels. SPORT Register Maps Table XIII. DMCLK (Internal) Rate Divider Settings There are eight control registers for the AD73360L, each eight MCD2 MCD1...

  • Page 16: Decimation Rate Divider

    The individual functional blocks of the AD73360L can be enabled Multiplexing (TDM) format. When data is being read from the AD73360L each channel has a fixed time slot in which its data separately by programming the power control register CRC. It is transmitted.

  • Page 17: Operating Modes

    The serial clock will occur at a slower default sample rate, which is DMCLK/ (SCLK) is an output from the AD73360L and is used to define 2048, until Control Register B is programmed, after which the the serial transfer rate to the DSP’s Tx and Rx ports.

  • Page 18: Digital Interfacing

    TMS320C5x) or, where SPORT power-down is not to the AD73360L is forced to be synchronous with the output data required, it can be permanently strapped high using a suitable from the AD73360L.
  • Page 19 AD73360L SCLK SDOFS UNDEFINED DATA UNDEFINED DATA SDIFS CONTROL WORD CONTROL WORD Figure 15a. Interface Signal Timing for Program Mode Operation (Writing to a Register) SCLK SDOFS UNDEFINED DATA READ RESULT SDIFS REGISTER READ INSTRUCTION 0x7FFF OR CONTROL WORD Figure 15b. Interface Signal Timing for Program Mode Operation (Reading a Register)

  • Page 20: Cascade Operation

    Cascade Operation In Cascade Mode, both devices must know the number of devices The AD73360L has been designed to support two devices in a in the cascade to be able to output data at the correct time. cascade connected to a single serial port (see Figure 17). The Control Register A contains a 3-bit field (DC0–2) that is pro-...

  • Page 21: Performance

    Figure 19. SE and RESET Sync Circuit for Cascaded Operation –80 PERFORMANCE –100 As the AD73360L is designed to provide high-performance, low-cost conversion, it is important to understand the means by –120 which this high performance can be achieved in a typical appli- –140 cation.

  • Page 22: Encoder Group Delay

    0.1 µF or larger. The dc biasing of the input can then be accom- plished using resistors to REFOUT as in Figure 25. Encoder Group Delay The AD73360L implementation offers a very low level of group delay, which is given by the following relationship: VINPx Group Delay (Decimator) = Order ×...

  • Page 23: Digital Interface

    ANALOG GROUND As there are a number of variations of sample rate and clock speeds that can be used with the AD73360L in a particular appli- cation, it is important to select the best combination to achieve the desired performance. High-speed serial clocks will read the data...

  • Page 24: Dsp Sport Interrupts

    AD73360L. motor control applications. A block diagram of a vector motor control application using the AD73360L is shown in Figure 30. The position of the field is derived by determining the current in each phase of the motor. THREE-...

  • Page 25: Appendix A (Single Device Data Mode Operation)

    Step 6 puts the AD73360L is in Program Mode the data transmitted will be the AD73360L into Data Mode and in Step 7 the first valid invalid ADC data and will, in fact, be a modified version of the ADC word is received.

  • Page 26: Appendix B (Single Device Mixed Mode Operation)

    DSP instructs the AD73360L to power up channels 1 and 2 Sync Loop-Back mode, care must be taken when writing to and sets the gain of each. No data is read from the AD73360L the AD73360L that an ADC result or register read result con- at this point.

  • Page 27: Appendix C (Two Devices In Data Mode Operation)

    Device 2 is outputting an invalid ADC word. (Note that Mode to Data Mode and the number of devices in the cascade is the AD73360L will not output valid ADC words until the device also programmed here. is placed in either mixed mode or data mode. Any ADC values In Step N + 2, we begin to receive valid ADC data.
  • Page 28 AD73360L DSP Tx REG DEVICE 1 DEVICE 2 DSP Rx REG ADC WORD 2* CONTROL WORD 1 ADC WORD 1* ADC WORD 2* 0000 0000 0000 0000 0000 0000 0000 0000 1000 1001 0000 0011 0000 0000 0000 0000 STEP 1...

  • Page 29: Appendix D (Two Devices In Mixed Mode Operation)

    This control word set the Device count to 2 and instructs the only one output event per sample period. The DSP can now AD73360L to go into Mixed Mode. When Device 1 receives send a control word to the AD73360Ls.
  • Page 30 AD73360L DSP Tx REG DEVICE 1 DEVICE 2 DSP Rx REG CONTROL WORD 1 ADC WORD 1* ADC WORD 2* DON'T CARE xxxx xxxx xxxx xxxx 1000 1001 0000 0011 0000 0000 0000 0000 0000 0000 0000 0000 STEP 1...

  • Page 31: Appendix E (Histograms Of Snr Results)

    AD73360L APPENDIX E HISTOGRAMS OF SNR RESULTS = 8kHz = 8kHz = 1kHz = 1kHz SCLK = 16MHz SCLK = 8MHz –83 –82 –81 –80 –79 –78 –84 –83 –82 –81 –80 –79 THD – dB THD – dB Figure 36. f...

  • Page 32: Table Of Contents

    FUNCTIONAL BLOCK DIAGRAM ....1 Resetting the AD73360L ......16 SPECIFICATIONS .

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