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FEATURES
Fast settling filter option
8 differential/16 pseudo differential input channels
RMS noise: 11 nV at 4.7 Hz (gain = 128)
15.5 noise-free bits at 2.4 kHz (gain = 128)
Up to 22 noise-free bits (gain = 1)
Offset drift: ±5 nV/°C
Gain drift: ±1 ppm/°C
Programmable gain (1 to 128)
Output data rate: 4.7 Hz to 4.8 kHz
Internal or external clock
Simultaneous 50 Hz/60 Hz rejection
4 general-purpose digital outputs
Power supply
AV
: 3 V to 5.25 V
DD
DV
: 2.7 V to 5.25 V
DD
Current: 4.65 mA
Temperature range: −40°C to +105°C
Package: 32-lead LFCSP
Interface
3-wire serial
SPI, QSPI™, MICROWIRE™, and DSP compatible
Schmitt trigger on SCLK
APPLICATIONS
PLC/DCS analog input modules
Data acquisition
Strain gage transducers
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
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FUNCTIONAL BLOCK DIAGRAM
AV
AGND
DD
AIN1/P3
AIN2/P2
AIN3/P1/REFIN2(+)
AIN4/P0/REFIN2(–)
AIN5
MUX
AIN16
AINCOM
AGND
TEMP
SENSOR
8-Channel, 4.8 kHz, Ultralow Noise,
24-Bit Sigma-Delta ADC with PGA
Pressure measurement
Temperature measurement
Flow measurement
Weigh scales
Chromatography
Medical and scientific instrumentation
GENERAL DESCRIPTION
The AD7194 is a low noise, complete analog front end for high
precision measurement applications. It contains a low noise,
24-bit sigma-delta (Σ-Δ) analog-to-digital converter (ADC).
The on-chip low noise gain stage means that signals of small
amplitude can interface directly to the ADC.
The device can be configured to have eight differential inputs or
sixteen pseudo differential inputs. The on-chip 4.92 MHz clock
can be used as the clock source to the ADC or, alternatively, an
external clock or crystal can be used. The output data rate from
the part can be varied from 4.7 Hz to 4.8 kHz.
The device has a very flexible digital filter, including a fast
settling option. Variables such as output data rate and settling
time are dependent on the option selected. For applications that
require all conversions to be settled, the AD7194 includes zero
latency.
The part operates with a power supply from 3 V to 5.25 V. It
consumes a current of 4.65 mA, and it is housed in a 32-lead
LFCSP package.
DV
DGND
REFIN1(+)
REFIN1(–)
DD
AD7194
AV
DD
Σ-Δ
PGA
ADC
Figure 1.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
REFERENCE
DETECT
DOUT/RDY
SERIAL
INTERFACE
DIN
AND
CONTROL
SCLK
LOGIC
CS
CLOCK
CIRCUITRY
MCLK1 MCLK2
©2009 Analog Devices, Inc. All rights reserved.
AD7194
www.analog.com
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Table of Contents
Related Manuals for Analog Devices AD7194
Summary of Contents for Analog Devices AD7194
-
Page 1: Features
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. -
Page 2: Table Of Contents
AD7194 TABLE OF CONTENTS Features ....................1 Programmable Gain Array (PGA) ........... 30 Applications ..................1 Reference ..................30 General Description ................. 1 Reference Detect ................. 31 Functional Block Diagram .............. 1 Bipolar/Unipolar Configuration .......... -
Page 3: Specifications
AD7194 SPECIFICATIONS = 3 V to 5.25 V, DV = 2.7 V to 5.25 V, AGND = DGND = 0 V; REFINx(+) = +2.5 V or AV , REFINx(−) = AGND, MCLK = 4.92 MHz, T to T , unless otherwise noted. - Page 4 AD7194 Parameter Unit Test Conditions/Comments Normal Mode Rejection Sinc Filter Internal Clock @ 50 Hz, 60 Hz 10 Hz output data rate, 50 Hz ± 1 Hz, 60 Hz ± 1 Hz 50 Hz output data rate, REJ60 = 1, 50 Hz ±...
- Page 5 AD7194 Parameter Unit Test Conditions/Comments REFERENCE INPUT REFIN Voltage REFIN = REFINx(+) − REFINx(−), the differential input must be limited to ±(AV − 1.25 V)/gain when gain > 1 Absolute REFIN Voltage AGND − 0.05 + 0.05 Limits Average Reference Input μA/V...
- Page 6 AD7194 Parameter Unit Test Conditions/Comments SYSTEM CALIBRATION Full-Scale Calibration Limit 1.05 × FS Zero-Scale Calibration −1.05 × FS Limit Input Span 0.8 × FS 2.1 × FS POWER REQUIREMENTS Power Supply Voltage − AGND 5.25 − DGND 5.25 Power Supply Currents Current 0.85...
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Page 7: Timing Characteristics
AD7194 TIMING CHARACTERISTICS = 3 V to 5.25 V, = 2.7 V to 5.25 V, AGND = DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = , unless otherwise noted. Table 2. 1, 2 Parameter... - Page 8 AD7194 Circuit and Timing Diagrams (1.6mA WITH DV = 5V, SINK 100µA WITH DV = 3V) OUTPUT 1.6V 50pF (200µA WITH DV = 5V, SOURCE 100µA WITH DV = 3V) Figure 2. Load Circuit for Timing Characterization CS (I) DOUT/RDY (O)
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Page 9: Absolute Maximum Ratings
AD7194 ABSOLUTE MAXIMUM RATINGS = 25°C, unless otherwise noted. THERMAL RESISTANCE θ is specified for the worst-case conditions, that is, a device Table 3. soldered in a circuit board for surface-mount packages. Parameter Rating to AGND −0.3 V to +6.5 V Table 4. -
Page 10: Pin Configuration And Function Descriptions
AD7194 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AIN1/P3 24 DV AIN2/P2 23 AV AIN3/P1/REFIN2(+) 22 DGND AD7194 AIN4/P0/REFIN2(–) 21 AGND TOP VIEW AINCOM 20 AIN16 (Not to Scale) 19 AIN15 AGND AIN5 18 REFIN1(–) AIN6 17 REFIN1(+) NOTES 1. NC = NO CONNECT. - Page 11 Logic input that allows for synchronization of the digital filters and analog modulators when using a number of AD7194 devices. While SYNC is low, the nodes of the digital filter, the filter control logic, and the calibration control logic are reset, and the analog modulator is also held in its reset state. SYNC does not affect the digital interface but does reset RDY to a high state if it is low.
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Page 12: Typical Performance Characteristics
AD7194 TYPICAL PERFORMANCE CHARACTERISTICS 8,387,952 8,387,950 8,387,948 8,387,946 8,387,944 8,387,942 8,387,940 8,387,938 8,387,936 8,387,934 1000 8,388,830 8,388,860 8,388,890 8,388,920 SAMPLE CODE Figure 6. Noise (V = AV = 5 V, Output Data Rate = 4.7 Hz, Figure 9. Noise Distribution Histogram (V... - Page 13 AD7194 –1 –2 –60 –40 –20 –4 –3 –2 –1 TEMPERAUTRE (°C) Figure 12. INL (Gain = 1) Figure 15. Offset vs. Temperature (Gain = 128, Chop Disabled) 1.000008 1.000006 1.000004 1.000002 1.000000 0.999998 0.999996 –5 0.999994 –10 0.999992 –15 0.999990...
- Page 14 AD7194 GAIN = 1 GAIN = 8 GAIN = 16 GAIN = 32 GAIN = 64 GAIN = 128 GAIN = 1 GAIN = 8 GAIN = 16 GAIN = 32 GAIN = 64 GAIN = 128 OUTPUT DATA RATE (Hz) OUTPUT DATA RATE (Hz) Figure 20.
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Page 15: Rms Noise And Resolution
(peak-to-peak) resolution of to note that the effective resolution is calculated using the rms the AD7194 for various output data rates and gain settings with noise, whereas the peak-to-peak resolution is calculated based chop disabled for the sinc... -
Page 16: Sinc 3 Chop Disabled
AD7194 SINC CHOP DISABLED Table 9. RMS Noise (nV) vs. Gain and Output Data Rate Gain of Output Data Settling Filter Word (Decimal) Rate (Hz) Time (ms) 1023 639.4 1100 1200 1900 2700 3.13 6400 2400 1.25 115,000 14,000 7000... -
Page 17: Fast Settling
AD7194 FAST SETTLING Table 12. RMS Noise (nV) vs. Gain and Output Data Rate Gain of Filter Word Output Data Settling (Decimal) Rate (Hz) Time (ms) Average 2.63 118.75 42.10 23.75 1500 50.53 19.79 1600 126.32 7.92 2700 252.63 3.96 3700 Table 13. -
Page 18: On-Chip Registers
AD7194 ON-CHIP REGISTERS The ADC is controlled and configured via a number of on-chip registers that are described on the following pages wherein the term, set, implies a Logic 1 state and cleared implies a Logic 0 state, unless otherwise noted. -
Page 19: Communications Register
AD7194 COMMUNICATIONS REGISTER a reset, the ADC is in this default state waiting for a write operation to the communications register. In situations where the RS2, RS1, RS0 = 000 interface sequence is lost, a write operation of at least 40 serial The communications register is an 8-bit write-only register. -
Page 20: Status Register
AD7194 STATUS REGISTER load Bit RS2, Bit RS1, and Bit RS0 with 0. Table 18 outlines the bit designations for the status register. SR0 through SR7 indicate the RS2, RS1, RS0 = 000; Power-On/Reset = 0x80 bit locations, SR denoting that the bits are in the status register. -
Page 21: Mode Register
MR19, MR18 CLK1, CLK0 These bits select the clock source for the AD7194. Either the on-chip 4.92 MHz clock or an external clock can be used. The ability to use an external clock allows several AD7194 devices to be synchronized. Also, 50 Hz/60 Hz rejection is improved when an accurate external clock drives the AD7194. - Page 22 MR11 Single Single cycle conversion enable bit. When this bit is set, the AD7194 settles in one conversion cycle so that it functions as a zero latency ADC. This bit has no effect when multiple analog input channels are enabled or when the single conversion mode is selected. If the fast-settling filter is enabled, this bit (single) does not have an effect on the conversions unless chopping is also enabled.
- Page 23 Idle mode. In idle mode, the ADC filter and modulator are held in a reset state even though the modulator clocks continue to be provided. Power-down mode. In power-down mode, all AD7194 circuitry is powered down. The external crystal, if selected, remains active.
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Page 24: Configuration Register
AD7194 CONFIGURATION REGISTER Table 21 outlines the bit designations for the configuration register. CON0 through CON23 indicate the bit locations. CON denotes RS2, RS1, RS0 = 010; Power-On/Reset = 0x000117 that the bits are in the configuration register. CON23 denotes The configuration register is a 24-bit register from which data the first bit of the data stream. - Page 25 CON18 Pseudo Pseudo differential analog inputs. When the pseudo bit is set to 1, the AD7194 is configured to have 16 pseudo differential analog inputs with AINCOM as the common negative terminal. Bits CH7 to CH4 select the positive input terminal while bits CH3 to CH0 have no effect. When the pseudo bit is set to 0, channel selection is controlled using the CH7 to CH0 bits.
- Page 26 AD7194 Channel Selection (Pseudo Bit = 0) Table 22. Positive Input Selection Table 23. Negative Input Selection Positive Input Enable Bits in Negative Input Enable Bits in the Positive Status Negative the Configuration Register Configuration Register Input Enabled Register Bits...
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Page 27: Data Register
ID REGISTER RS2, RS1, RS0 = 100; Power-On/Reset = 0xX3 The identification number for the AD7194 is stored in the ID register. This is a read-only register. 0(0) 0(0) -
Page 28: Offset Register
The calibrated full-scale calibration coefficient, the calibration being AD7194 must be placed in power-down mode or idle mode performed at gain = 1. Therefore, every device has different when writing to the offset register. -
Page 29: Adc Circuit Information
The AD7194 has an internal 4.92 MHz clock. Either this clock device. Because the multiplexer is included on chip, any channel or an external clock can be used as the clock source to the AD7194. changes are synchronized with the conversion process. -
Page 30: Analog Input Channel
AVDD resolution. AIN16 The AD7194 can be programmed to have a gain of 1, 8, 16, 32, 64, and 128 by using Bit G2 to Bit G0 in the configuration register. Therefore, with an external 2.5 V reference, the AVDD unipolar ranges are from 0 mV to 19.53 mV to 0 V to 2.5 V,... -
Page 31: Reference Detect
If AINCOM is 2.5 V and the AD7194 AIN1 analog input is configured for bipolar mode with a gain of 2, the analog input Recommended 2.5 V reference voltage sources for the AD7194... -
Page 32: Digital Interface
The serial interface can be reset by writing a series of 1s to the or DOUT/ RDY ) occur with respect to the SCLK signal. DIN input. If a Logic 1 is written to the AD7194 DIN line for at least 40 serial clock cycles, the serial interface is reset. This... - Page 33 DOUT/ RDY goes high. If CS is low, DOUT/ RDY remains high until another conversion is initiated and completed. The data In single conversion mode, the AD7194 is placed in power- register can be read several times, if required, even when down mode after conversions.
- Page 34 Continuous conversion is the default power-up mode. The pletion of the next conversion or else the new conversion word AD7194 converts continuously, and the RDY bit in the status is lost. register goes low each time a conversion is complete. If CS is...
- Page 35 Rather than write to the communications register each time a or if insufficient serial clocks are applied to the AD7194 to conversion is complete to access the data, the AD7194 can be...
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Page 36: Reset
AD7194 into a consistent, known state. While the CLK0 bits in the mode register. When an external crystal is SYNC pin is low, the AD7194 is maintained in this state. On the used, it must be connected across the MCLK1 and MCLK2 SYNC rising edge, the modulator and filter are taken out of this pins. -
Page 37: Logic Outputs
CALIBRATION To perform an internal full-scale calibration, a full-scale input The AD7194 provides four calibration modes that can be pro- voltage is automatically connected to the selected analog input grammed via the mode bits in the mode register. These modes for this calibration. - Page 38 The gain error of the AD7194 is factory calibrated at a gain of 1 The AD7194 gives the user access to the on-chip calibration with a 5 V power supply at ambient temperature. Following this registers, allowing the microprocessor to read the calibration calibration, the gain error is ±0.001%, typically, at 5 V.
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Page 39: Digital Filter
AD7194 DIGITAL FILTER The AD7194 offers a lot of flexibility in the digital filter. The When conversions are performed on a single channel and a device has five filter options. The device can be operated with step change occurs, the ADC does not detect the change in... - Page 40 AD7194 When the analog input is constant or a channel change occurs, Figure 32 shows the frequency response when FS[9:0] is valid conversions are available at a constant output data rate. programmed to 80 and the master clock is equal to 4.92 MHz.
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Page 41: Sinc 3 Filter (Chop Disabled)
AD7194 The output data rate is 50 Hz when zero latency is disabled and The 3 dB frequency is equal to 12.5 Hz when zero latency is enabled. Figure 34 shows the = 0.272 × f frequency response of the sinc filter. - Page 42 AD7194 The output data rate equals Sinc 50 Hz/60 Hz Rejection Figure 39 show the frequency response of the sinc filter when = 1/t /(3 × 1024 × FS[9:0]) SETTLE FS[9:0] is set to 96 and the master clock equals 4.92 MHz. The...
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Page 43: Chop Enabled (Sinc Filter)
AD7194 Simultaneous 50 Hz and 60 Hz rejection is obtained when CHOP ENABLED (SINC FILTER) FS[9:0] is set to 480 (master clock = 4.92 MHz), as shown in With chop enabled, the ADC offset and offset drift are minimized. Figure 41. The output data rate is 10 Hz when zero latency is The analog input pins are continuously swapped. - Page 44 AD7194 When a channel change occurs, the modulator and filter reset. –10 The complete settling time is required to generate the first –20 conversion after the channel change. Subsequent conversions –30 on this channel occur at 1/f –40 –50 CHANNEL A...
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Page 45: Chop Enabled (Sinc Filter)
AD7194 CHOP ENABLED (SINC FILTER) If conversions are performed on a single channel and a step change occurs, the ADC does not detect the change in analog With chop enabled, the ADC offset and offset drift are input; therefore, it continues to output conversions at the minimized. -
Page 46: Fast Settling Mode (Sinc Filter)
AD7194 The 50 Hz/60 Hz rejection can be improved by setting the The settling time is equal to REJ60 bit in the mode register to 1. With FS[9:0] set to 96 and = 1/f SETTLE REJ60 set to 1, the filter response shown in Figure 52 is achieved. - Page 47 AD7194 of 42.10 Hz when the master clock equals 4.92 MHz. The sinc Simultaneous 50 Hz/60 Hz rejection is achieved when FS[9:0] is filter places the first notch at set to 30 and the postfilter averages by 16. The output data rate is equal to 8.4 Hz whereas the rejection at 50 Hz ±...
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Page 48: Fast Settling Mode (Sinc Filter)
AD7194 FAST SETTLING MODE (SINC FILTER) If the analog input channel is changed, there is no additional delay in generating valid conversions and the device functions In fast settling mode, the settling time is close to the inverse of as a zero latency ADC. - Page 49 AD7194 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 –120 FREQUENCY (Hz) FREQUENCY (Hz) Figure 63. Filter Response for Average + Decimate Filter Figure 65. Filter Response for Average + Decimate Filter...
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Page 50: Fast Settling Mode (Chop Enabled)
AD7194 FAST SETTLING MODE (CHOP ENABLED) input pins and the averaging of subsequent conversions means that the offset drift is also minimized. Chop can be enabled in the fast settling mode. With chop Chopping does not change the output data rate. However, the enabled, the ADC offset and offset drift are minimized. -
Page 51: Summary Of Filter Options
Table 36 shows some sample configurations and the corresponding performance in terms of throughput, settling The AD7194 has several filter options. The filter that is chosen time and 50 Hz/60 Hz rejection. affects the output data rate, settling time, the rms noise, the stop band attenuation, and the 50 Hz/60 Hz rejection. -
Page 52: Grounding And Layout
AD7194 to prevent noise coupling. The power at the modulator sampling frequency. A 100 Ω resistor in series supply lines to the AD7194 must use as wide a trace as possible with each analog input, a 0.1 μF capacitor between the analog to provide low impedance paths and reduce the effects of input pins, and a 0.01 μF capacitor from each analog input to... -
Page 53: Applications Information
(it is the ratio of the precision reference resistance to the thermistor FLOWMETER resistance that is measured). Figure 67 shows the AD7194 being used in a flowmeter application For simplicity, external filters are not shown in Figure 67; that consists of two pressure transducers with the rate of flow however, an R-C antialias filter must be included on each analog being equal to the pressure difference. -
Page 54: Outline Dimensions
AD7194 OUTLINE DIMENSIONS 5.10 0.30 5.00 SQ 0.25 4.90 0.18 PIN 1 INDICATOR 0.50 3.65 EXPOSED 3.50 SQ 3.45 0.50 0.25 MIN TOP VIEW BOTTOM VIEW 0.40 0.30 FOR PROPER CONNECTION OF 0.80 THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND 0.75... - Page 55 AD7194 NOTES Rev. 0 | Page 55 of 56 Downloaded from Elcodis.com electronic components distributor...
- Page 56 AD7194 NOTES ©2009 Analog Devices, Inc. All rights reserved. Trademarks and ©2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. registered trademarks are the property of their respective owners. D08566-0-10/09(0) Rev. 0 | Page 56 of 56 Downloaded from Elcodis.com...
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