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FEATURES
Dynamic performance
DOCSIS 3.0 performance
8 QAM carriers @ 400 MHz IF: −71 dBc
16 QAM carriers @ 400 MHz IF: −68 dBc
32 QAM carriers @ 400 MHz IF: −65 dBc
72 QAM carriers @ 600 MHz IF: −61 dBc
Single-carrier WCDMA ACLR performance @ 2457.6 MSPS
f
= 350 MHz (normal mode)
OUT
st
1
adjacent channel: −80 dBc
5
th
adjacent channel: −80.5 dBc
f
= 2100 MHz (mix mode)
OUT
st
1
adjacent channel: −69 dBc
th
5
adjacent channel: −75 dBc
Single-tone NSD performance @ 2.4 GSPS
−166 dBm/Hz @ 100 MHz IF
−162 dBm/Hz @ 1 GHz IF
RF synthesis support
FS mix, RZ modes
Dual-port LVDS data interface with on-chip 100 Ω
terminations
Low power: 1.1 W @ 2.5 GSPS
APPLICATIONS
Broadband communications systems
CMTS/VOD
Cellular infrastructure
Point-to-point wireless
Instrumentation, automatic test equipment
Radar, avionics
GENERAL DESCRIPTION
The AD9739 is a high performance, high frequency 14-bit DAC
that provides sample rates up to 2500 MSPS, permitting
multicarrier generation up to the Nyquist frequency in
baseband mode and second and third Nyquist zones in mix
mode. It includes a serial peripheral interface (SPI) for
configuration and readback of status registers. A dual-port
LVDS interface is used to enable the high sample rate with
existing FGPA/ASIC technology. The output current can be
programmed over a range of 8.66 mA to 31.66 mA. The
AD9739 is manufactured on a 0.18 μm CMOS process and
operates from 1.8 V and 3.3 V supplies. It is supplied in a 160-
ball chip scale ball grid array for reduced package parasitics.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
14-Bit, 2500 MSPS,
RF Digital-to-Analog Converter
FUNCTIONAL BLOCK DIAGRAM
RESET
SDIO
SDO
SPI
CS
SCLK
DCO_P
DCO_N
SYNC_OUT_P
SYNC_OUT_N
DCI_P
DCI_N
SYNC_IN_P
SYNC_IN_N
DB0[13:0]P
DB0[13:0]N
DB1[13:0]P
DB1[13:0]N
SPI
PRODUCT HIGHLIGHTS
1.
Low noise and intermodulation distortion (IMD)
performance enable high quality synthesis of wideband
signals up to 1 GHz.
2.
A dual-port interface with double data rate (DDR) LVDS
data receivers supports the maximum conversion rate of
2500 MSPS.
3.
Manufactured on a CMOS process, the AD9739 uses a
proprietary switching technique that enhances dynamic
performance.
4.
The current output(s) of the AD9739 are easily configured
for single-ended or differential circuit topologies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
©2009-2011 Analog Devices, Inc. All rights reserved.
AD9739
DACCLK_N DACCLK_P
CLOCK
DISTRIBUTION
14-, 12-,
10-BIT DAC
CORE
REFERENCE
BAND GAP
CURRENT
S2
VREF
I120
Figure 1.
www.analog.com
IOUTP
IOUTN
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Table of Contents
Related Manuals for Analog Devices AD9739
Summary of Contents for Analog Devices AD9739
-
Page 1: Features
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. -
Page 2: Table Of Contents
LVDS Data Port Interface............37 Revision History ................2 Clocking the AD9739 ..............39 Specifications..................3 Applying Data to the AD9739 ..........40 DC Specifications ................. 3 Mu Delay Controller..............41 Digital Specifications ..............4 Mu Control Operation............... -
Page 3: Specifications
AD9739 SPECIFICATIONS DC SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, I = 20 mA. Table 1. Parameter Unit RESOLUTION Bits ACCURACY Integral Nonlinearity (INL) ±1.3 Differential Nonlinearity (DNL) ±0.8 ANALOG OUTPUTS Gain Error (with Internal Reference) Full-Scale Output Current 8.66... -
Page 4: Digital Specifications
AD9739 DIGITAL SPECIFICATIONS VDDA = VDD33 = 3.3 V, VDDC = VDD = 1.8 V, I = 20 mA. LVDS drivers and receivers are compliant to the IEEE-1596 reduced range link, unless otherwise noted. Table 2. Parameter Unit LVDS DATA INPUTS (DB0[13:0]P, DB0[13:0]N, DB1[13:0]P, DB1[13:0]N) DB+ = V , DB−= V... -
Page 5: Ac Specifications
AD9739 Parameter Unit INPUTS (SDI, SDIO, SCLK, CS) Voltage in High, V Voltage in Low, V Current in High, I −10 μA Current in Low, I −10 μA SDIO Output Voltage Out High, V Voltage Out Low, V Current Out High, I... - Page 6 = 2457.6 MSPS, f = 3600 MHz 64.5 Adjusted DAC updated rate is calculated as f divided by the minimum required interpolation factor. For the AD9739, the minimum interpolation factor is 1. Thus, with f = 2500 MSPS, f adjusted = 2500 MSPS.
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Page 7: Absolute Maximum Ratings
AD9739 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. θ is specified for the worst-case conditions, that is, a device With Parameter Respect To Rating soldered in a circuit board for surface-mount packages. VDDA VSSA −0.3 V to +3.6 V Table 5. Thermal Resistance VDD33 −0.3 V to +3.6 V... -
Page 8: Pin Configurations And Function Descriptions
AD9739 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS VDDC, 1.8V, CLOCK SUPPLY VDDA, 3.3V, ANALOG SUPPLY VSSA, ANALOG SUPPLY GROUND VSSC, CLOCK SUPPLY GROUND VSSA SHIELD, ANALOG SUPPLY GROUND SHIELD Figure 2. Analog Supply Pins (Top View) Figure 4. Digital LVDS Clock Supply Pins (Top View) - Page 9 I120 VREF IPTAT RESET SDIO SCLK Figure 6. Analog I/O and SPI Control Pins (Top View) Table 6. AD9739 Pin Function Descriptions Pin No. Mnemonic Description C1, C2, D1, D2, E1, E2, E3, E4 VDDC 1.8 V Clock Supply. A1, A2, A3, A4, A5, B1, B2, B3, B4, B5, C4, VSSC Clock Supply Ground.
- Page 10 AD9739 Pin No. Mnemonic Description L1, M1 DB1[0]P/DB1[0]N Port 1 Positive/Negative Data Input Bit 0. L2, M2 DB1[1]P/DB1[1]N Port 1 Positive/Negative Data Input Bit 1. L3, M3 DB1[2]P/DB1[2]N Port 1 Positive/Negative Data Input Bit 2. L4, M4 DB1[3]P/DB1[3]N Port 1 Positive/Negative Data Input Bit 3.
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Page 11: Typical Performance Characteristics
AD9739 TYPICAL PERFORMANCE CHARACTERISTICS STATIC LINEARITY –0.5 –1.0 –0.5 –1.5 –1.0 –1.5 –2.0 –2.0 –2.5 –2.5 –3.0 –3.0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE CODE Figure 7. Typical INL, 20 mA @ 25°C Figure 10. - Page 12 AD9739 –0.5 –0.5 –1.0 –1.0 –1.5 –1.5 –2.0 –2.0 –2.5 –2.5 –3.0 –3.0 2048 4096 6144 8192 10,240 12,288 14,336 16,384 2048 4096 6144 8192 10,240 12,288 14,336 16,384 CODE CODE Figure 13. Typical INL, 10 mA @ 25°C Figure 16. Typical DNL, 30 mA @ 25°C TOTAL –0.5...
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Page 13: Dynamic Performance Normal Mode, 20 Ma Full Scale (Unless Otherwise Noted)
AD9739 DYNAMIC PERFORMANCE NORMAL MODE, 20 MA FULL SCALE (UNLESS OTHERWISE NOTED) –6dBFS –3dBFS 0dBFS 1000 START 20MHz STOP 2.4GHz VBW 10kHz (MHz) Figure 18. Single Tone Spectrum @ f = 91 MHz, f = 2.4 GSPS Figure 21. SFDR vs. f over DIGFS @ 2.0 GSPS... - Page 14 AD9739 –6dBFS 30mA FS 10mA FS 0dBFS –3dBFS 20mA FS 1000 1000 (MHz) (MHz) Figure 24. SFDR vs. f over ANAFS @ 2.0 GSPS Figure 27. IMD vs. f over DIGFS @ 2.0 GSPS 20mA FS +85°C –40°C 10mA FS +25°C...
- Page 15 AD9739 –150 –150 –152 –152 –154 –154 –156 –156 –158 –158 2.4GSPS –160 –160 –162 –162 –40°C –164 –164 1.2GSPS –166 –166 +85°C –168 –168 +25°C –170 –170 100 200 300 400 500 600 700 800 900 1000 1100 1200...
- Page 16 AD9739 CENTER 350.27MHz SPAN 53.84MHz CENTER 355.11MHz SPAN 63.84MHz #RES BW 30kHz SWEEP 174.6ms (601pts) #RES BW 30kHz SWEEP 207ms (601pts) VBW 300kHz VBW 300kHz FREQ FREQ RMS RESULTS OFFSET LOWER UPPER RMS RESULTS LOWER UPPER OFFSET (MHz) (MHz) (dBc)
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Page 17: Dynamic Performance Mix Mode, 20 Ma Full Scale
AD9739 DYNAMIC PERFORMANCE MIX MODE, 20 mA FULL SCALE START 20MHz STOP 2.4GHz 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 #RES BW 10kHz SWEEP 28.7s (601pts) VBW 10kHz (MHz) Figure 37. Single-Tone Spectrum in Mix Mode @ f = 2.31 GHz,... - Page 18 AD9739 CENTER 2.807GHz SPAN 53.84MHz CENTER 2.81271GHz SPAN 63.84MHz #RES BW 30kHz SWEEP 174.6ms (601pts) #RES BW 30kHz SWEEP 207ms (601pts) VBW 300kHz VBW 300kHz FREQ FREQ RMS RESULTS RMS RESULTS OFFSET LOWER UPPER OFFSET LOWER UPPER (MHz) (MHz) (dBc)
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Page 19: Docsis Performance
AD9739 DOCSIS PERFORMANCE –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 1000 1000 (MHz) (MHz) Figure 46. Single-Carrier DOCSIS ACLR Spectral Plot @ 91 MHz Figure 49. Single-Carrier DOCSIS ACLR Spectral Plot @ 325 MHz (DOCSIS SPEC (Red Line) Is 73 dBc ;... - Page 20 AD9739 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –90 –80 1000 1000 (MHz) (MHz) Figure 52. Single-Carrier DOCSIS ACLR Spectral Plot @ 825 MHz (DOCSIS SPEC Figure 55. Four-Carrier DOCSIS ACLR Spectral Plot @ 91 MHz (DOCSIS SPEC (Red Line) Is 73 dBc ;...
- Page 21 AD9739 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 1000 1000 (MHz) (MHz) Figure 58. Four-Carrier DOCSIS ACLR Spectral Plot @ 325 MHz (DOCSIS SPEC Figure 61. Four-Carrier DOCSIS ACLR Spectral Plot @ 825 MHz (DOCSIS SPEC (Red Line) Is 67 dBc ;...
- Page 22 AD9739 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 1000 1000 (MHz) (MHz) Figure 64. Eight-Carrier DOCSIS ACLR Spectral Plot @ 100 MHz Figure 67. 16-Carrier DOCSIS ACLR Spectral Plot @ 400 MHz (DOCSIS SPEC (Red Line) Is 63 dBc;...
- Page 23 AD9739 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 1000 1000 (MHz) (MHz) Figure 70. 32-Carrier DOCSIS ACLR Spectral Plot @ 900 MHz Figure 72. 72-Carrier DOCSIS ACLR Spectral Plot @ 700 MHz (DOCSIS SPEC (Red Line) Is 57 dBc; Harmonic Exception Is 42 dBc) (DOCSIS SPEC (Red Line) Is 54 dBc;...
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Page 24: Terminology
AD9739 TERMINOLOGY Linearity Error (Integral Nonlinearity or INL) Power Supply Rejection The maximum deviation of the actual analog output from the The maximum change in the full-scale output as the supplies ideal output, determined by a straight line drawn from zero to are varied from nominal to minimum and maximum specified full scale. -
Page 25: Theory Of Operation
AD9739 THEORY OF OPERATION The AD9739 is a 14-bit DAC that operates at an update rate of The remaining SCLK edges are for Phase 2 of the communication up to 2.5 GSPS. Due to internal timing requirements, the cycle. Phase 2 is the actual data transfer between the AD9739 minimum allowable sample rate is 800 MSPS. -
Page 26: Msb/Lsb Transfers
After the last instruction bit is written to the SDIO pin, the driving signal must be set to a high impedance in time for the SCLK bus to turn around. The serial output data from the AD9739 is enabled by the falling edge of SCLK. This causes the first output SDIO... -
Page 27: Spi Register Map
AD9739 SPI REGISTER MAP Table 7. Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default Mode 0x00 SDIO_DIR LSB/MSB Reset 0x00 Power- 0x01 LVDS_DCO LVDS_RCVR CLK_REC_ DAC_BIAS 0x00 Down CNT_CLK_... -
Page 28: Spi Registers
AD9739 Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default LVDS_ 0x1F SYNCSH_ 0x00 DEL[0] REC_STAT7 LVDS_ 0x20 SYNCSH_ SYNCSH_ SYNCSH_ SYNCSH_ SYNCSH_ SYNCSH_ SYNCSH_ SYNCSH_ 0x00 DEL[8] DEL[7] DEL[6]... - Page 29 AD9739 Table 11. Power-Down Register Bit Descriptions Reset Value for Bit Name Read/Write Description Write Register LVDS_DCO_PD Read/write 0: DCO enabled. 1: DCO disabled. LVDS_RCVR_PD Read/write 0: LVDS receiver enabled. 1: LSB receiver powered down. CLK_REC_PD Read/write 0: internal clock receiver enabled.
- Page 30 AD9739 Reset Value for Bit Name Read/Write Description Write Register MULCK_IRQ Read 0: the mu controller is unlocked. 1: the mu controller has achieved lock and an interrupt has occurred. RCVLST_IRQ Read 0: the RCV controller has not lost lock.
- Page 31 AD9739 Table 21. LVDS Control/Status Register Bit Descriptions Reset Value for Bit Name Read/Write Description Write Register Read/write HNDOFF_CHK_RST 0: default. Bit is in the inactive state. 0x00 1: resets the handoff errors in Register 0x0B. LVDS_Bias[1:0] Read/write 0x0: 360 μA bias current.
- Page 32 AD9739 Table 22. LVDS Receiver Control Registers (Register 0x10, Register 0x11, Register 0x12, Register 0x13, Register 0x14, Register 0x15, Register 0x16, Register 0x17, Register 0x18) Register Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...
- Page 33 AD9739 Table 24. LVDS Receiver Status Registers (Register 0x19, Register 0x1A, Register 0x1B, Register 0x1C, Register 0x1D, Register 0x1E, Register 0x1F, Register 0x20, Register 0x21) Register Name Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2...
- Page 34 AD9739 Reset Value for Bit Name Read/Write Description Write Register RCVR_FE_ON Read 0: indicates that the FINDEDGE state machine is not active. 1: indicates that the FINDEDGE state machine is active. RCVR_LST_LCK Read 0: lock has not been lost. 1: lock has been lost at some point.
- Page 35 AD9739 Table 29. MU Controller Register Bit Descriptions Reset Value for Bit Name Read/Write Description Write Register PHS_DET Read/write 0: no action. AUTO_EN 1: enables phase detector correction (recommended to always enable). CMP_BST Read/write 0: no action. 1: enables the phase detector comparator boost (only valid if PHS_DET AUTO_EN is enabled;...
- Page 36 AD9739 Reset Value for Bit Name Read/Write Description Write Register Retry Read/write 0x0: if the correct value is not found, the search stops. 0x1: if the correct value is not found, the search begins again. Search_Tol Read/write 0x0: not exact (can find a phase within two values of the desired phase).
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Page 37: Applications Information
ZERO MODE) DBx[13:0] Figure 82. Mix Mode and RZ DAC Waveforms This ability to change modes in the AD9739 makes it suitable Figure 80. AD9739 Quad-Switch Architecture for both CMTS and UMTS applications. The user can place a The quad-switch architecture masks the code-dependent glitches carrier anywhere in the first three Nyquist zones, depending on that occur in a conventional two-switch DAC. - Page 38 AD9739 The SYNC_IN_x and SYNC_OUT_x signals are used to The data receiver behaves like a shift register with a variable synchronize multiple parts (see the Synchronization Controller delay from one register to the next. The data receiver uses the section for more information). Each data port runs internally at...
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Page 39: Clocking The Ad9739
To provide the required signal swing for the internal clock 1.4 VPP. The maximum allowable clock frequency is 2.5 GSPS and, receiver of the AD9739, it is necessary to use an external clock due to internal timing requirements for the part, the minimum buffer chip to drive the DACCLK_P and DACCLK_N inputs. -
Page 40: Applying Data To The Ad9739
DB0[13:0]P DB0[13:0]N DEINTERLEAVE DB0, DB1, DB2, IOUTP 14-BIT, 12-BIT, FILE DB3, DB4... 10-BIT DAC CORE IOUTN DB1, DB3, DB5... DB1[13:0]P DB1[13:0]N Figure 87. Graphical Representation of How to Present Data to the AD9739 Rev. A | Page 40 of 56... -
Page 41: Mu Delay Controller
AD9739 MU DELAY CONTROLLER measured, the slope of the phase measurement is calculated and compared against the desired slope, which is specified by the The mu delay controller adjusts timing between the digital and Slope bit in Register 0x26. A positive slope occurs when the analog blocks. -
Page 42: Track Mode
AD9739 To determine the correct slope, the controller measures the Mu Delay and Phase Readback slope by first incrementing and then decrementing the mu delay By setting the read bit high (Register 0x26, Bit 3), the user can value until any of the following happens: read back the mu delay value that the controller locked to by •... -
Page 43: Synchronization Controller
AD9739 SYNCHRONIZATION CONTROLLER proper SYNC_IN_x position. The synchronization circuitry has two modes of operation, master and slave. In master mode, the A top level diagram of the synchronization circuitry and sync operation starts an initialization phase that determines the controller is shown in Figure 92. The synchronization circuitry... -
Page 44: Operation In Master Mode
AD9739 PHASE 0 Operation in Master Mode Setting Register 0x10, Bit 5 high sets the controller to master SYNC_IN_x mode. This enables the sync logic to enter an initialization PHASE 1 phase that adjusts the SYNC_OUT_x delay. By moving the Figure 93. -
Page 45: Operation In Slave Mode
AD9739 CONTROLLER SYNC_IN_x PHASE CLOCK Figure 95. Slave Mode Tracking Mode Block Diagram Status bits are available in the SPI to verify that the synchron- the controller then enters tracking mode. The starting delay ization controller has found lock (Register 0x21, Bit 4), that... -
Page 46: Data Receiver Operation In Manual Mode
AD9739 by the DCI transition detection, and then back into track mode. between these flip flops in the data path. If the timing in any Status bits are available in the SPI to verify that the receiver one of these stages is violated, one of the status bits in Register... -
Page 47: Optimizing The Clock Common-Mode Voltage
−15 on both the CLKP and CLKN offset bits. Figure 101. 1/f Noise with Respect to the MSEL Bits VOLTAGE REFERENCE The AD9739 output current is set by a combination of CLKx_OFFSET digital control bits and the I120 reference current, as shown DIR_x = 0 in Figure 102. -
Page 48: Analog Outputs
Always connect a 10 kΩ resistor from the I120 pin to ground and use the digital controls to vary the full-scale current. The AD9739 is not a multiplying DAC. Applying an analog signal to I120 is not supported. VREF (Pin C14) must be bypassed to ground with a 1 nF capacitor. -
Page 49: Interrupt Requests
There following six interrupt requests (IRQ) can be used for differential amplifier configuration. Internal to the AD9739 is a additional verification of the status of each controller.: differential resistance between IOUTP and IOUTN that must •... -
Page 50: Recommended Start-Up Sequence
AD9739 RECOMMENDED START-UP SEQUENCE The steps necessary to optimize the performance of the part and generate an output waveform are as follows: Enable clocks to the controller and set the full-scale current. The registers and bits used in this step are shown in Table 35. - Page 51 AD9739 Table 40. Recommended Register Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value PHS_DET 0x24 PHS_DET CMP_BST Bias[3] Bias[2] Bias[1] Bias[0] 0x30 AUTO_EN (1) MU_DUTY 0x25 MU_DUTY POS/NEG (0) ADJ[5](0)
- Page 52 AD9739 To verify that the sync controller is locked and tracking, the following bits must be read back: • Register 0x21, Bit 4 (SYNC_LCK)—If the controller is locked, this bit reads back a value of 1. This is a value of 1 for the master part only.
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Page 53: Outline Dimensions
AD9739 OUTLINE DIMENSIONS 12.10 12.00 SQ A1 BALL 11.90 CORNER A1 BALL CORNER 10.40 BSC SQ 0.80 BOTTOM VIEW TOP VIEW 1.00 MAX DETAIL A DETAIL A 0.85 MIN 0.43 MAX 1.40 MAX 0.25 MIN 0.55 COPLANARITY SEATING 0.20 0.50 PLANE 0.45... - Page 54 AD9739 NOTES Rev. A | Page 54 of 56...
- Page 55 AD9739 NOTES Rev. A | Page 55 of 56...
- Page 56 AD9739 NOTES ©2009-2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07851-0-7/11(A) Rev. A | Page 56 of 56...
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