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SIMPLIFIED BLOCK DIAGRAM
R
SENSE
+
C
C
IN2
IN1
+
IN
A = N
SW0
V
ADJ
OUT1
TO 1.8V
UP TO 50A
V
OUT0
C
C
2.2µF
OUT2
OUT1
GND
0.01µF
TSNS0b
TSNS0a
+
V
OSNS0
REMOTE SENSE
LOAD0
C
LOAD0
–
V
OSNS0
COMP0b
C
COMPH
COMP0a
C
COMPL
PGOOD0
SCL
SDA
ALERT
5.5V-TOLERANT
WP
PULL-UP NOT
SHOWN
RUN0
RUN1
FAULT0
3.3V-TOLERANT
FAULT1
PULL-UP NOT
SHARE_CLK
SHOWN
DECOUPLING REQUIREMENTS
SYMBOL
PARAMETER
C
External High Frequency Input Capacitor Requirement
INH
(5.75V ≤ V
≤ 16V, V
IN
C
External High Frequency Output Capacitor Requirement
OUTn
(5.75V ≤ V
≤ 16V, V
IN
–
SV
IN
V
IN
IN0
1µF
4.7µF
0.22µF
INPUT CURRENT/ICHIP (READIIN,
MFRREADIINPEAK TO ANALOG
READBACK)
SV
IN
MT0
150nH
MB0
TSNS0
TO ANALOG
I
CURRENT SENSE
OUT0
READBACK
X1
PROG GM
+
EA0
–
22pF
PROG R
COMP
POWER CONTROL DIGITAL SECTION
ROM
RAM
Figure 2. Simplified LTM4700 Block Diagram
Commanded to 1.000V)
OUTn
Commanded to 1.000V)
OUTn
For more information
2.2µF
INTV
RUNP
V
V
CC
DD33
IN1
2.2µF
1µF
5V BIAS
CONV.
1µF
INTV
EXTV
CC
CC
MT1
POWER CONTROL
ANALOG SECTION
MB1
DIE TEMP SENSE
TO ANALOG
I
CURRENT SENSE
OUT0
READBACK
TEMP MUX
ALL ANALOG
READBACK SIGNALS
PROG GM
+
10:1 MUX
EA1
–
ADC
SPI SLAVE
SPI MASTER
SYNC DRIVER
DIGITAL ENGINE
32MHz OSC
EEPROM
T
= 25°C. Using Figure 2 configuration.
A
CONDITIONS
I
= 50A
OUT0
I
= 50A
OUT1
I
= 50A
OUT0
I
= 50A
OUT1
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LTM4700
22µF
V
BIAS
SW1
150nH
V
OUT1
2.2µF
GND
0.01µF
SGND
TSNS1
TSNS1b
TSNS1a
+
V
+
OSNS1
X1
REMOTE SENSE
–
V
–
OSNS1
COMP1b
22pF
PROG R
COMP
COMP1a
PGOOD1
3.3V
SYNC
TOLERANT PULL-UP
NOT SHOWN
V
DD25
2.5V
2.2µF
ASEL
FSWPH_ CFG
VTRIM0_ CFG
CONFIG RESISTORS
VTRIM1_ CFG
TO SGND NOT SHOWN
VOUT0_CFG
VOUT1_CFG
4700 F02
MIN
TYP
88
88
800
800
V
ADJ
OUT1
TO 1.8V
UP TO 50A
C
C
OUT4
OUT3
C
LOAD1
LOAD1
C
COMPH
C
COMPL
MAX
UNITS
µF
µF
µF
µF
Rev. B
19
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