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Channel C-High Pulse Duty Register 1
The
and
PWM_CH0
PWM_CH1
see the
PWM_CH0
register description.
Figure 19-57: PWM_CH1 Register Diagram
Table 19-35: PWM_CH1 Register Fields
Bit No.
(Access)
15:0
DUTY
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
registers determine the width for the high side output pulses. For more information,
15
14
13
0
0
0
DUTY (R/W)
Duty Cycle De-Asserted Count
31
30
29
0
0
0
Bit Name
Duty Cycle De-Asserted Count.
The PWM_CH1.DUTY bits select the duty cycle de-asserted count for Channel C high
side output.
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
28
27
26
25
24
23
22
21
20
0
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x PWM Register Descriptions
4
3
2
1
0
0
0
0
0
0
19
18
17
16
0
0
0
0
0
19–75
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