Analog Devices ADSP-SC58 Series Hardware Reference Manual page 999

ADSP-SC58x PWM Register Descriptions
Table 19-37: PWM_CHANCFG Register Fields
Bit No.
(Access)
30 ENCHOPDL
(R/W)
29 POLDL
(R/W)
28 ENHPDH
(R/W)
27 ENCHOPDH
(R/W)
26 POLDH
(R/W)
19–78
Bit Name
Channel D Gate Chopping Enable Low Side.
The PWM_CHANCFG.ENCHOPDL bit enables mixing of the Channel D low side out-
put signals with a high-frequency chopping signal, which is configured with the
PWM_CHOPCFG
Channel D low side Polarity.
The PWM_CHANCFG.POLDL bit selects the Channel D low side output polarity (ac-
tive-high or active-low).
Channel D heightened-precision enable for high side Output.
The PWM_CHANCFG.ENHPDH bit enables heightened-precision Channel D high side
output.
Channel D Gate Chopping Enable High Side.
The PWM_CHANCFG.ENCHOPDH bit enables mixing of the Channel D high side
output signals with a high-frequency chopping signal, which is configured with the
PWM_CHOPCFG
Channel D High side Polarity.
The PWM_CHANCFG.POLDH bit selects the Channel D high side output polarity (ac-
tive-high or active-low).
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
register.
0 Disable Chopping Channel D Low Side
1 Enable Chopping Channel D Low Side
0 Active Low
1 Active High
0 Disable HP Output Channel D High
1 Enable HP Output Channel D High
register.
0 Disable Chopping Channel D High Side
1 Enable Chopping Channel D High Side
0 Active Low
1 Active High