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part of the cache-line fill executes on the tenth cycle; the second instruc-
tion executes on the eleventh cycle, and the third instruction executes on
the twelfth cycle—all of them in parallel with the cache line fill.
Each cache line fill is aligned on a 32-byte boundary. When the requested
instruction or data is not 32-byte aligned, the requested item is always
loaded in the first read; each read is forwarded to the core as the line is
filled. Sequential memory accesses miss the cache only when they reach
the end of a cache line.
When on-chip L2 memory is configured as non-cacheable, instruction
fetches and data fetches occur in 64-bit fills. In this case, each fill takes
seven core cycles to complete. As shown in
on-chip L2 memory is configured as non-cacheable. To illustrate the con-
cept of L2 latency with cache off, simple instructions are used that do not
require additional external data fetches. In this case, consecutive instruc-
tions are issued on consecutive core cycles if multiple instructions are
brought into the core in a given fetch.
Memory Protection and Properties
This section describes the Memory Management Unit (MMU), memory
pages, CPLB management, MMU management, and CPLB registers.
Memory Management Unit
The Blackfin processor contains a page based Memory Management Unit
(MMU). This mechanism provides control over cacheability of memory
ranges, as well as management of protection attributes at a page level. The
MMU provides great flexibility in allocating memory and I/O resources
between tasks, with complete control over access rights and cache
behavior.
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
Figure 6-17 on page
Memory
6-46,
6-45
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