Mapping Faults To Fault Pins; Power Good Pins; Crc Protection; Serial Interface - Analog Devices Linear LTM 4700 User Manual

OPERATION

Mapping Faults to FAULT Pins

Channel-to-channel fault (including channels from multiple
LTM4700s) dependencies can be created by connecting
FAULTn pins together. In the event of an internal fault, one
or more of the channels is configured to pull the bussed
FAULTn pins low. The other channels are then configured
to shut down when the FAULTn pins are pulled low. For
autonomous group retry, the faulted channel is config-
ured to let go of the FAULTn pin(s) after a retry interval,
assuming the original fault has cleared. All the channels
in the group then begin a soft-start sequence. If the fault
response is LATCH_OFF, the FAULTn pin remains asserted
low until either the RUN pin is toggled OFF/ON or the part
is commanded OFF/ON. The toggling of the RUN either
by the pin or OFF/ON command will clear faults associ-
ated with the channel. If it is desired to have all faults
cleared when either RUN pin is toggled or, set bit 0 of
MFR_CONFIG_ALL to a 1.
The status of all faults and warnings is summarized in the
STATUS_WORD and STATUS_BYTE commands.
Additional fault detection and handling capabilities are:

Power Good Pins

The PGOODn pins of the LTM4700 are connected to the
open drains of internal MOSFETs. The MOSFETs turn on
and pull the PGOODn pins low when the channel output
voltage is not within the channel's UV and OV voltage thresh-
olds. During TON_DELAY and TON_RISE sequencing, the
PGOODn pin is held low. The PGOODn pin is also pulled
low when the respective RUNn pin is low. The PGOODn pin
response is deglitched by an internal 100µs digital filter.
The PGOODn pin and PGOOD status may be different at
times due to communication latency of up to 10µs.

CRC Protection

The integrity of the NVM memory is checked after a power
on reset. A CRC error will prevent the controller from leav-
ing the inactive state. If a CRC error occurs, the CML bit is
set in the STATUS_BYTE and STATUS_WORD commands,
the appropriate bit is set in the STATUS_MFR_SPECIFIC
command, and the ALERT pin will be pulled low. NVM
repair can be attempted by writing the desired configura-
tion to the controller and executing a STORE_USER_ALL
command followed by a CLEAR_FAULTS command.
The LTM4700 manufacturing section of the NVM is mir-
rored. If both copies are corrupted, the "NVM CRC Fault"
in the STATUS_MFR_SPECIFIC command is set. If this bit
remains set after being cleared by issuing a CLEAR_FAULTS
or writing a 1 to this bit, an irrecoverable internal fault has
occurred. The user is cautioned to disable both output
power supply rails associated with this specific part.
There are no provisions for field repair of NVM faults in
the manufacturing section.

SERIAL INTERFACE

The LTM4700 serial interface is a PMBus compliant slave
device and can operate at any frequency between 10kHz
and 400kHz. The address is configurable using either the
NVM or an external resistor divider. In addition the LTM4700
always responds to the global broadcast address of 0x5A
(7-bit) or 0x5B (7-bit).
The serial interface supports the following protocols de-
fined in the PMBus specifications: 1) send command, 2)
write byte, 3) write word, 4) group, 5) read byte, 6) read
word and 7) read block. 8) write block. All read operations
will return a valid PEC if the PMBus master requests it. If
the PEC_REQUIRED bit is set in the MFR_CONFIG_ALL
command, the PMBus write operations will not be acted
upon until a valid PEC has been received by the LTM4700.

Communication Protection

PEC write errors (if PEC_REQUIRED is active), attempts
to access unsupported commands, or writing invalid data
to supported commands will result in a CML fault. The
CML bit is set in the STATUS_BYTE and STATUS_WORD
commands, the appropriate bit is set in the STATUS_CML
command, and the ALERT pin is pulled low.

DEVICE ADDRESSING

The LTM4700 offers four different types of addressing
over the PMBus interface, specifically: 1) global, 2) device,
3) rail addressing and 4) alert response address (ARA).
For more information www.analog.com
LTM4700
Rev. B
35