Mapping Faults To Faultn Pins; Power Good Pins; Crc Protection; Serial Interface - Analog Devices LTM4683 Manual

LTM4683
OPERATION

Mapping Faults to FAULTn Pins

Channel-to-channel fault (including channels from mul-
tiple LTM4683s) dependencies can be created by con-
necting FAULTn pins together. In the event of an internal
fault, one or more of the channels is configured to pull the
bussed FAULTn pins low. The other channels are config-
ured to shut down when the FAULTn pins are pulled low.
For autonomous group retry, the faulted channel is con-
figured to let go of the FAULTn pin(s) after a retry interval,
assuming the original fault has cleared. All the channels
in the group, then begins a soft-start sequence. If the
fault response is LATCH_OFF, the FAULTn pin remains
asserted low until either the RUNn pin is toggled Off/On
or the part is commanded Off/On. Either toggling of the
RUNn pin or Off/On command will clear faults associ-
ated with the channel. If it is desired to have all faults
cleared when either the RUNn pin is toggled or set bit 0
of MFR_CONFIG_ALL to a 1.
The status of all faults and warnings is summarized in the
STATUS_WORD and STATUS_BYTE commands.
Additional fault detection and handling capabilities include
power good pins and cyclic redundancy check (CRC).

Power Good Pins

The PGOODn pins of the LTM4683 are connected to the
open drains of internal MOSFETs. The MOSFET turns on and
pulls the PGOODn pin low when the channel output voltage
is not within the channel's UV and OV voltage threshold
ranges. During TON_DELAY and TON_RISE sequencing,
the PGOODn pin is held low. The PGOODn pin is also pulled
low when the respective RUNn pin is low. The PGOODn pin
response is deglitched by an internal 100µs digital filter. The
PGOODn pin and PGOOD status can be different at times
due to communication latency of up to 10µs.

CRC Protection

The integrity of the NVM memory is checked after a power
on reset. A CRC error will prevent the controller from leav-
ing the inactive state. If a CRC error occurs, the CML bit is
set in the STATUS_BYTE and STATUS_WORD commands,
the appropriate bit is set in the STATUS_MFR_SPECIFIC
40
command, and the ALERT_nn pin will be pulled low. NVM
repair can be attempted by writing the desired configura-
tion to the controller and executing a STORE_USER_ALL
command followed by a CLEAR_FAULTS command.
The LTM4683 manufacturing section of the NVM is
mirrored. If both copies are corrupted, the "NVM CRC
Fault" in the STATUS_MFR_SPECIFIC command is set.
If this bit remains set after being cleared by issuing a
CLEAR_ FAULTS or writing a 1 to this bit, an irrecoverable
internal fault has occurred. The user is cautioned to dis-
able both output power supply rails associated with this
specific part. There are no provisions for field repair of
NVM faults in the manufacturing section.

SERIAL INTERFACE

The LTM4683 serial interface is a PMBus-compliant
subordinate device and can operate at any frequency
between 10kHz and 400kHz. The address is configurable
using either the NVM or an external resistor. In addition,
the LTM4683 always responds to the global broadcast
address of 0x5A (7-bit) or 0x5B (7-bit).
The serial interface supports the following protocols
defined in the PMBus specifications: 1) send command,
2) write byte, 3) write word, 4) group, 5) read byte, 6)
read word, and 7) read block. 8) write block. All read
operations will return a valid PEC if the PMBus main
device requests it. If the PEC_REQUIRED bit is set in the
MFR_ CONFIG_ ALL command, the PMBus write opera-
tions will not be acted upon until a valid PEC has been
received by the LTM4683.

Communication Protection

PEC write errors (if PEC_REQUIRED is active), attempts
to access unsupported commands, or writing invalid data
to supported commands will result in a CML fault. The
CML bit is set in the STATUS_BYTE and STATUS_WORD
commands, the appropriate bit is set in the STATUS_CML
command, and the ALERT pin is pulled low.
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