STMicroelectronics SPEAr300 Manuals

STMicroelectronics SPEAr300 Manuals

Manuals and User Guides for STMicroelectronics SPEAr300. We have 1 STMicroelectronics SPEAr300 manual available for free PDF download: Reference Manual

STMicroelectronics SPEAr300 Reference Manual

STMicroelectronics SPEAr300 Reference Manual (844 pages)

Brand: STMicroelectronics | Category: Microcontrollers | Size: 6 MB

Table of Contents

Table of Contents
2
Acronyms

52
- Table 1. Acronyms
  52
Preface

54
- Terms & Conditions
  54
- Conventions
  54
  - Numbering
    54
  - Bits
    54
  - Typographical
    54
  - Table 2. Typographical Conventions
    54
Reference Documentation

55
Product Overview

56
- Device Overview
  56
  - Figure 1. Spear300 Top View
    56
  - Main Features
    57
- Architecture Properties
  58
- System Architecture Overview
  59
  - Core Architecture
    59
  - Figure 2. Spear300 - Core Architecture Overview
    59
- CPU Subsystem
  60
- Multilayer Bus Matrix
  60
- Dynamic Memory Controller
  60
- Basic Subsystem
  61
- High Speed Connectivity Subsystem
  61
- Low Speed Connectivity Subsystem
  61
- Application Subsystem
  62
- Reconfigurable Logic Array Subsystem
  62
- Clock and Reset System
  63
Pin Description

64
Memory Map

82
CPU Subsystem_Arm926Ej-S

85
- Overview
  85
- Functional Description
  86
- Main Function Description
  86
  - Memory Management Unit
    86
  - Figure 4. ARM926EJ-S Block Diagram
    86
  - Caches and Write Buffer
    87
  - Bus Interface Unit
    87
CPU Subsystem_Vectored Interrupt Controller (VIC)

89
Bus Interconnection Matrix

103
- Table 49. Soc Interconnection Matrix Scheme
  103
- Table 50. Soc Interconnection Matrix
  103
- ICM
  104
- Table 51. ICM Master Layers (Initiator)
  104
- Figure 6. ICM Block Diagram
  104
- Table 52. ICM Slaves (Targets)
  105
DDR Memory Controller (MPMC)

106
Ls_Analog to Digital Convertor (ADC)

643
- Operating Sequence
  644
Rs_Reconfigurable Array Subsystem (RAS) Registers

652
Rs_General Purpose Input Output (GPIO)

815
Power and Clock Management

816
Bootrom

826
- Figure 112. Boot Stages
  827
- Booting Pins
  827
- Figure 113. Hardware Memory
  828
- Hardware Overview
  828
- Software Overview
  829
- Boot Flows
  830
  - Figure 114. Boot Flows
    831
  - Serial nor Flash Boot
    831
  - Figure 115. Serial nor Flash Boot
    832
  - NAND Flash Boot
    832
  - Figure 116. NAND Flash Boot
    833
  - Table 744. Command Format
    834
  - USB Boot
    834
  - Table 745. Device Descriptors
    835
  - Table 746. Configuration Registers
    835
  - Table 747. Interface Registers
    836
  - Table 748. Bulk out Endpoint
    836
  - Table 749. Bulk in Endpoint
    836
  - Table 750. String Descriptors
    837
  - Figure 117. USB Boot
    838
  - Serial (UART) Boot
    839
  - Figure 118. Serial Boot
    840
  - Ethernet Boot
    841
  - Figure 119. Ethernet Boot
    842
  - Table 751. Document Revision History
    843

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