Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1000

Table 19-37: PWM_CHANCFG Register Fields (Continued)
Bit No.
(Access)
25 MODELSD
(R/W)
24 REFTMRD
(R/W)
22 ENCHOPCL
(R/W)
21 POLCL
(R/W)
20 ENHPCH
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Channel D Mode of low Side Output.
The PWM_CHANCFG.MODELSD bit selects whether the low side output waveform is
based on independent controls or whether the low side output depends on the high
side output controls. When PWM_CHANCFG.MODELSD =0, the low side output is an
inverted form of the high side output, which is generated using the
PWM_BH1
pulse positioning, and PWM_CHANCFG.POLBH bits for polarity.
Channel D Timer Reference.
The PWM_CHANCFG.REFTMRD bit selects whether the PWM uses PWMTMR1 or
PWMTMR0 as the reference timer for Channel D operation.
Channel C Gate Chopping Enable Low Side.
The PWM_CHANCFG.ENCHOPCL bit enables mixing of the Channel C low side out-
put signals with a high-frequency chopping signal, which is configured with the
PWM_CHOPCFG
Channel C low side Polarity.
The PWM_CHANCFG.POLCL bit selects the Channel C low side output polarity (ac-
tive-high or active-low).
Channel C heightened-precision enable for high side Output.
The PWM_CHANCFG.ENHPCH bit enables heightened-precision Channel C high side
output.
Description/Enumeration
registers for pulse width, using the PWM_BCTL.PULSEMODEHI bits for
0 Invert of high output
1 Independent control
0 PWMTMR0 is Channel D reference
1 PWMTMR1 is Channel D reference
register.
0 Disable Chopping Channel C Low Side
1 Enable Chopping Channel C Low Side
0 Active Low
1 Active High
0 Disable HP Output Channel C High
1 Enable HP Output Channel C High
ADSP-SC58x PWM Register Descriptions
PWM_BH0 and
19–79