Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1009

ADSP-SC58x PWM Register Descriptions
Chop Configuration Register
The register holds a divisor value that controls the chopping frequency. The PWM permits a mix-
PWM_CHOPCFG
ing of the output signals with a high-frequency chopping signal to aid with interfacing to pulse transformers. Also
note that high-frequency chopping may be independently enabled for each channel's high-side and the low-side out-
puts using channel control bits. (For example, control chopping for Channel A with the
PWM_CHANCFG.ENCHOPAH and PWM_CHANCFG.ENCHOPAH bits.)
Figure 19-64: PWM_CHOPCFG Register Diagram
Table 19-42: PWM_CHOPCFG Register Fields
Bit No.
(Access)
7:0 VALUE
(R/W)
19–88
15 14 13
0 0 0
VALUE (R/W)
Gate Chopping Divisor
31 30 29
0 0 0
Bit Name
Gate Chopping Divisor.
The PWM_CHOPCFG.VALUE bits provide the high frequency chopping divisor.
When the divisor value is changed, the new period takes effect from the next edge of
the chopping signal. The PWM_CHOPCFG.VALUE value may be calculated using ei-
ther of the following formulas:
CHOPDIV = [(T
CHOPDIV = [(f
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
12 11 10 9 8 7 6 5
0 0 0 0 0 0 0 0
28 27 26 25 24 23 22 21
0 0 0 0 0 0 0 0
Description/Enumeration
/T ) / 4] - 1
CHOP CK
/ f ) / 4] - 1
CK CHOP
4 3 2 1 0
0 0 0 0 0
20 19 18 17 16
0 0 0 0 0