Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1004

Table 19-37: PWM_CHANCFG Register Fields (Continued)
Bit No.
(Access)
1 MODELSA
(R/W)
0 REFTMRA
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Channel A Mode of low Side Output.
The PWM_CHANCFG.MODELSA bit selects whether the low side output waveform is
based on independent controls or whether the low side output depends on the high
side output controls. When PWM_CHANCFG.MODELSA =0, the low side output is an
inverted form of the high side output, which is generated using the
PWM_AH1
pulse positioning, and PWM_CHANCFG.POLAH bits for polarity.
Channel A Timer Reference.
The PWM_CHANCFG.REFTMRA bit selects whether the PWM uses PWMTMR1 or
PWMTMR0 as the reference timer for Channel A operation.
Description/Enumeration
registers for pulse width, using the PWM_ACTL.PULSEMODEHI bits for
0 Invert of high output
1 Independent control
0 PWMTMR0 is Channel A reference
1 PWMTMR1 is Channel A reference
ADSP-SC58x PWM Register Descriptions
PWM_AH0 and
19–83