Operating States - Altera Cyclone V Device Handbook

16-4

Operating States

The DMAC has eight DMA channels. Each channel supports a single concurrent thread of DMA operation.
In addition, a single DMA manager thread exists, and you can use it to initialize the DMA channel threads.
The DMAC executes up to one instruction per clock cycle. To ensure that it regularly executes each active
thread, the DMAC alternates by processing the DMA manager thread and then a DMA channel thread. It
performs a round-robin process when selecting the next active DMA channel thread to execute.
The DMAC uses variable-length instructions that consist of one to six bytes. It provides a separate program
counter (PC) register for each DMA channel. When a thread requests an instruction from an address, the
cache performs a lookup. If a cache hit occurs, then the cache immediately provides the instruction. Otherwise,
the thread is stalled while the DMAC performs a cache line fill with the AXI master interface. If an instruction
spans the end of a cache line, the DMAC performs multiple cache accesses to fetch the instruction.
Note: When a cache line fill is in progress, the DMAC enables other threads to access the cache. But if
another cache miss occurs, the pipeline stalls until the first line fill is complete.
When a DMA channel thread executes a load or store instruction, the DMAC adds the instruction to the
relevant read or write queue. The DMAC uses these queues as an instruction storage buffer prior to it issuing
the instructions on the AXI. The DMAC also contains an MFIFO data buffer in which it stores data that it
reads, or writes, during a DMA transfer.
The DMAC provides multiple interrupt outputs to enable efficient communication of events to external
microprocessors. The peripheral request interfaces support the connection of DMA-capable peripherals to
enable memory-to-peripheral and peripheral-to-memory DMA transfers to occur, without intervention
from a microprocessor.
Dual slave interfaces enable the operation of the DMAC to be partitioned into the Secure state and Non-
secure states. You can access status registers and also directly execute instructions in the DMAC with the
slave interfaces.
Operating States
The following figure shows the transitions among operating states for the DMA manager thread and DMA
channel threads. The DMAC provides a separate state machine for each thread.
The DMAC provides a separate state machine for each thread.
Altera Corporation
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2013.12.30
DMA Controller
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