Peripheral Request Interface - Altera Cyclone V Device Handbook

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Peripheral Request Interface

• Instruction byte 0 encoding for DMAGO.

• Instruction byte 1 encoding for DMAGO.

• Debug thread bit to 0 to select the DMA manager thread.

c. Write to the DBGINST1 register with the DMAGO instruction byte [5:2] data. You must set these four

bytes to the address of the first instruction in the program, that is written to system memory in the

step 2 above.

4. Instruct the DMAC to execute the instruction that the debug instruction registers contain by writing

zero to the DBGCMD register. The DMAC starts the DMA channel thread and sets the dbgstatus bit

to 1. After the DMAC completes execution of the instruction, it clears the dbgstatus bit to 0.

Peripheral Request Interface

The following figure shows that the peripheral request interface consists of a peripheral request bus and a

DMAC acknowledge bus that use the prefixes:

• dr The peripheral request bus

• da The DMAC acknowledge bus

Figure 16-3: Request and Acknowledge Buses on the Peripheral Request Interface

The peripheral indicates the following on the request bus:

• Request a single transfer

• Request a burst transfer

• Acknowledge a flush request

The peripheral indicates the DMAC when it issues the last request of the DMA transfer sequence.

The DMAC can indicate the following on the acknowledge bus:

• Indicate when it completes the requested single transfer

• Indicate when it completes the requested burst transfer

• Issue a flush request

You can assign a peripheral request interface to any of the DMA channels. When a DMA channel thread

executes DMAWFP, the value programmed in the peripheral [4:0] field specifies the peripheral associated

with that DMA channel.

The DMAC supports 31 peripheral request handshakes. Each request handshake can receive up to four

outstanding requests, and is assigned a specific peripheral device ID. The following table lists the peripheral

device ID assignments.

Altera Corporation

DMA Controller

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