Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1034

Channel A Delay Register
The register controls a delay for the Channel A timer (only PWMTMR1, PWMTMR2, PWMTMR3
PWM_DLYA
or PWMTMR4) with reference to the main timer (PWMTMR0). To use apply this delay, the delay must be enabled
(PWM_CTL.DLYAEN =1). For more information about applying the delay, see the PWM Functional Description
section. Note that the PWM_DLYA
used for the channel (for example, if PWMTMR1 is used,
note that the period of the main timer must be an integer multiple of the timer being used for the channel (for
example, if PWMTMR1 is used, PWMTMR0 = NxPWMTMR1, where N is an integer).
Figure 19-85: PWM_DLYA Register Diagram
Table 19-63: PWM_DLYA Register Fields
Bit No.
(Access)
15:0 VALUE
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
delay value must be less that less that twice the period value of the timer being
15 14 13
0 0 0
VALUE (R/W)
Channel A Delay Value
31 30 29
0 0 0
Bit Name
Channel A Delay Value.
The PWM_DLYA.VALUE bits select the phase delay between the main timer
(PWMTMR0) and the timer used for Channel A.
must be less than 2xPWMTMR1). Also,
PWM_DLYA
12 11 10 9 8 7 6 5
0 0 0 0 0 0 0 0
28 27 26 25 24 23 22 21
0 0 0 0 0 0 0 0
Description/Enumeration
ADSP-SC58x PWM Register Descriptions
4 3 2 1 0
0 0 0 0 0
20 19 18 17 16
0 0 0 0 0
19–113