Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1030

Channel D-Low Pulse Duty Register 0
The and
PWM_DL0 PWM_DL1
registers select the assertion count (in terms of t
The operation of the duty-cycle registers varies, depending on the pulse mode selected with the
PWM_DCTL.PULSEMODELO bits. When the pulse mode is symmetrical, the PWM uses the value in the
register to determine the assertion and deassertion count for the low side output pulses. When the pulse
PWM_DL0
mode is asymmetrical, left half, or right half, the PWM asserts channel D low pulse output for count less than
PWM_DL0 and deasserts this output for count greater than PWM_DL1.
The value range for the
channel. For example, if
ment) and +PWM_TM0/2, when dead time (PWM_CHD_DT) is not considered.
When dead time is considered for symmetrical and asymmetrical pulse modes, the value range for
PWM_DL1 depends on the period of the time being used by the channel and the amount of dead time applied to the
channel. For example, if
(two's complement) and +PWM_TM0/2 + PWM_CHD_DT.
When dead time is considered for left half or right half pulse modes, if
be between PWM_TM0/2 +
Note that using values in the
under modulation.
For more information about pulse modes and duty cycle selection, see the Functional Description section.
Figure 19-81: PWM_DL0 Register Diagram
Table 19-59: PWM_DL0 Register Fields
Bit No.
(Access)
15:0 DUTY
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
registers determine the width for the low side output pulses. The values in these
PWM_DL0 and PWM_DL1
is used, the duty cycle values may be between -PWM_TM0/2 (two's comple-
PWM_TM0
is used, the duty cycle values may be between -PWM_TM0/2 +
PWM_TM0
(two's complement) and -PWM_TM0/2 - PWM_CHD_DT.
PWM_CHD_DT
or
PWM_DL0 PWM_DL1
15 14 13
0 0 0
DUTY (R/W)
Duty Cycle Asserted Count
31 30 29
0 0 0
Bit Name
Duty Cycle Asserted Count.
The PWM_DL0.DUTY bits select the duty cycle asserted count for Channel D low
side output.
) of the low side output pulses for the channel D duty cycle.
CK
registers depends on the period of the timer being used by the
registers that fall outside these limits causes PWM over or
12 11 10 9 8 7 6 5
0 0 0 0 0 0 0 0
28 27 26 25 24 23 22 21
0 0 0 0 0 0 0 0
Description/Enumeration
ADSP-SC58x PWM Register Descriptions
PWM_TM0 is used, the duty cycle values may
4 3 2 1 0
0 0 0 0 0
20 19 18 17 16
0 0 0 0 0
PWM_DL0 and
PWM_CHD_DT
19–109