Aborts - Altera Cyclone V Device Handbook

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2013.12.30
For example, if the DMAC executes DMASEV 6 and none of the other threads have executed DMAWFE 6,
the event remains pending. If the DMAC executes DMAWFE 6 instruction for channel 4 and then executes
DMAWFE 6 instruction for channel 3, the following actions occur:
1. The DMAC halts execution of the channel 4 thread for one clock cycle.
2. The DMAC clears event 6.
3. The DMAC resumes execution of the channel 4 thread.
4. The DMAC halts execution of the channel 3 thread and the thread stalls while it waits for the next
occurrence of event 6.
Interrupting the MPU Subsystem
The DMAC provides the irq[x] signals for use as active-high level-sensitive interrupts to the MPU
subsystem. When you program the INTEN register to generate an interrupt, after the DMAC executes
DMASEV, it sets the corresponding irq[x] signal high.
The MPU subsystem can clear the interrupt by writing to the INTCLR register.
Note: Executing DMAWFE does not clear an interrupt.
If you use the DMASEV instruction to notify a microprocessor when the DMAC completes a DMALD or
DMAST instruction then you should insert a memory barrier instruction before the DMASEV. Otherwise the
DMAC might signal an interrupt before the AXI transfers complete.
The following program shows the example of Memory Barrier Instruction.
DMALD
DMAST
# Issue a write memory barrier
# Wait for the AXI write transfer to complete before the DMAC
# can send an interrupt
DMAWMB
# The DMAC sends the interrupt
DMASEV

Aborts

Abort Types
An abort can be classified as either precise or imprecise, depending on whether the DMAC provides an abort
handler with the precise state of the DMAC when the abort occurs.
• Precise AbortThe DMAC updates the PC register with the address of the instruction that created the
abort.
• Imprecise AbortThe PC register might contain the address of an instruction which did not cause the
abort to occur.
DMA Controller
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Interrupting the MPU Subsystem
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