Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1048

Table 19-71: PWM_STAT Register Fields (Continued)
Bit No.
(Access)
5 SRTRIPA
(R/NW)
4 FLTTRIPA
(R/W1C)
3 RAWTRIP1
(R/NW)
2 RAWTRIP0
(R/NW)
1 TRIP1
(R/W1C)
0 TRIP0
(R/W1C)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Self-Restart Trip Status for Channel A.
The PWM_STAT.SRTRIPA bit indicates whether the PWM Channel A self-restart
has been tripped. For more information, see the PWM_TRIPCFG.MODE0A bit de-
scription.
Fault Trip Status for Channel A.
The PWM_STAT.FLTTRIPA bit indicates whether the PWM Channel A fault has
been tripped. For more information, see the PWM_TRIPCFG.MODE0A bit descrip-
tion.
Raw Trip 1 Status.
The PWM_STAT.RAWTRIP1 bit indicates the raw input level for the PWM TRIP1
input.
Raw Trip 0 Status.
The PWM_STAT.RAWTRIP0 bit indicates the raw input level for the PWM TRIP0
input.
Status bit set when TRIP1 is active low.
The PWM_STAT.TRIP1 bit indicates whether the PWM TRIP1 fault has been trip-
ped with an active-low input.
Status bit set when TRIP0 is active low.
The PWM_STAT.TRIP0 bit indicates whether the PWM TRIP0 fault has been trip-
ped with an active-low input.
ADSP-SC58x PWM Register Descriptions
Description/Enumeration
0 Channel A Self-Restart Trip Status is "not tripped"
1 Channel A Self-Restart Trip Status is "tripped"
0 Channel A Fault Trip Status is "not tripped"
1 Channel A Fault Trip Status is "tripped"
0 TRIP1 Level is Low
1 TRIP1 Level is High
0 TRIP0 Level is Low
1 TRIP0 Level is High
0 TRIP1 status is "not tripped"
1 TRIP1 status is "tripped" (active low)
0 TRIP0 status is "not tripped"
1 TRIP0 status is "tripped" (active low)
19–127