Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1040

Interrupt Latch Register
The register latches the occurrence of unmasked (enabled) PWM interrupt requests. These interrupt
PWM_ILAT
requests are unmasked or masked with the
TRIP1 (R/W1C)
TRIP1 Interrupt Latched Status
TMR4PER (R/W1C)
PWMTMR4 Period Latched Interrupt
Status
TMR3PER (R/W1C)
PWMTMR3 Period Latched Interrupt
Status
TMR2PER (R/W1C)
PWMTMR2 Period Latched Interrupt
Status
Figure 19-91: PWM_ILAT Register Diagram
Table 19-69: PWM_ILAT Register Fields
Bit No.
(Access)
20 TMR4PER
(R/W1C)
19 TMR3PER
(R/W1C)
18 TMR2PER
(R/W1C)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
PWM_IMSK
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0 0
Bit Name
PWMTMR4 Period Latched Interrupt Status.
The PWM_ILAT.TMR4PER bit indicates the latched status of the PWMTMR4 peri-
od boundary interrupt request.
PWMTMR3 Period Latched Interrupt Status.
The PWM_ILAT.TMR3PER bit indicates the latched status of the PWMTMR3 peri-
od boundary interrupt request.
PWMTMR2 Period Latched Interrupt Status.
The PWM_ILAT.TMR2PER bit indicates the latched status of the PWMTMR2 peri-
od boundary interrupt request.
register.
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
Description/Enumeration
0 No Interrupt Latched
1 Interrupt Latched
0 No Interrupt Latched
1 Interrupt Latched
0 No Interrupt Latched
1 Interrupt Latched
ADSP-SC58x PWM Register Descriptions
TRIP0 (R/W1C)
TRIP0 Interrupt Latched Status
TMR0PER (R/W1C)
PWMTMR0 Period Boundary Interrupt
Latched Status
TMR1PER (R/W1C)
PWMTMR1 Period Latched Interrupt
Status
19–119