Programming Restrictions - Altera Cyclone V Device Handbook

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2013.12.30
a 4 KB address boundary, then the DMAC generates a pair of bursts with a combined length equal to that
specified. This operation is transparent to the DMAC channel thread program so that, for example, the
DMAC responds to a single DMALD instruction by generating the appropriate pair of AXI read bursts.
AXI Burst Types
You can program the DMAC to generate only fixed-address or incrementing-address burst types for data
accesses. It does not generate wrapping-address bursts for data accesses or for instruction fetches.
AXI Write Addresses
The DMAC can issue up to eight outstanding write addresses. The DMAC does not issue a write address
until it has read in all of the data bytes required to fulfill that write transaction.
AXI Write Data Interleaving
The DMAC does not generate interleaved write data. All write data beats for one write transaction are output
before any write data beat for the next write transaction.

Programming Restrictions

Certain restrictions apply when programming the DMAC.
Fixed Unaligned Bursts
The DMAC does not support fixed unaligned bursts. If you program the following conditions, the DMAC
treats this as a programming error:
• Unaligned read
• src_inc field is 0 in the CCRn register.
• The SARn register contains an address that is not aligned to the size of data that the
src_burst_size field contains.
• Unaligned write
• dst_inc field is 0 in the CCRn register.
• The DARn register contains an address that is not aligned to the size of data that the
dst_burst_size field contains.
Endian Swap Size Restrictions
If you program the endian_swap_size field in the CCRn register, to enable a DMA channel to perform
an endian swap, then you must set the corresponding SAR register and the corresponding DARn register to
contain an address that is aligned to the size that the endian_swap_size field specifies before executing
any DMALD or DMAST instructions.
Note:
If you update any of endian_swap_size, SARn , or DARn , for example, using a DMAADDH SAR
instruction, then you must ensure that the SARn and DARn registers contain an address aligned to
the size that the endian_swap_size field specifies before executing any additional DMALD or
DMAST instructions.
DMA Controller
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AXI Burst Types
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