Constraints And Limitations Of Use - Altera Cyclone V Device Handbook

16-22

Constraints and Limitations of Use

• DMAFLUSHP The DMAC uses the status of the corresponding PNS bit, in the CR4 register, to control
if it sends a flush request to the peripheral.
• If PNS = 0 The peripheral is in the Secure state. The DMAC:
• Executes an NOP.
• Sets the appropriate bit in the FSRC register that corresponds to the DMA channel number.
• Sets the ch_periph_err bit in the FTRn register.
• Moves the DMA channel to the Faulting completing state.
• If PNS = 1 The peripheral is in the Non-secure state. The DMAC clears the state of the peripheral
and sends a message to the peripheral to resend its level status.
When a DMA channel thread is in the Non-secure state, and a DMAMOV CCR instruction attempts to program
the channel to perform a secure AXI transaction, the DMAC:
1. Executes a DMANOP.
2. Sets the appropriate bit in the FSRC register that corresponds to the DMA channel number.
3. Sets the ch_rdwr_err bit in the FTRn register.
4. Moves the DMA channel thread to the Faulting completing state.
Constraints and Limitations of Use
DMA Channel Arbitration
The DMAC uses a round-robin scheme to serve the active DMA channels. To ensure that the DMAC
continues to serve the DMA manager, it always serves the DMA manager prior to serving the next DMA
channel.
You cannot alter the arbitration process of the DMAC.
DMA Channel Prioritization
The DMAC responds to all active DMA channels with equal priority. You cannot increase the priority of a
DMA channel over any other DMA channels.
Instruction Cache Latency
When a cache miss occurs, most of the delay is introduced by the memory containing the DMA code; the
DMAC adds minimal delay.
AXI Data Transfer Size
The DMAC can only perform data accesses up to 64 bits in width. If you program the src_burst_size
or dst_burst_size fields to be larger, the DMAC indicates a precise abort.
Related Information
Abort Sources
AXI Bursts Crossing 4 KB Boundaries
The AXI specification does not permit AXI bursts to cross 4 KB address boundaries. If you program the
DMAC with a combination of burst start address, size, and length that would cause a single burst to cross
Altera Corporation
on page 16-16
cv_54016
2013.12.30
DMA Controller
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