Security Usage - Altera Cyclone V Device Handbook
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Also See for Cyclone V:
- Technical reference (3536 pages) ,
- User manual (136 pages) ,
- Reference manual (66 pages)
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16-18
Security Usage
After an abort occurs, the action of the DMAC depends on the thread type:
• DMA channel thread The thread immediately moves to the Faulting completing state. In this state, the
DMAC performs the following operations:
• Sets the irq_abort signal high.
• Stops executing instructions for the DMA channel.
• Invalidates all cache entries for the DMA channel updates the CPC n register to contain the address
of the aborted instruction provided that the abort is precise.
• Does not generate AXI accesses for any instructions remaining in the read queue and write queue.
• Permits currently active AXI transactions to complete.
Note:
After the transactions for the DMA channel finish, the thread moves to the Faulting state.
• DMA manager thread The thread immediately moves to the Faulting state and the DMAC sets the
irq_abort signal high.
The external agent can respond to the assertion of the irq_abort signal by all of the following:
• Reading the status of the FSRD register to determine if the DMA manager is Faulting. In the Faulting
state, the FSRD register provides the cause of the abort.
• Reading the status of the FSRC register to determine if a DMA channel is Faulting. In the Faulting
state, the FSRC register provides the cause of the abort.
To enable a thread in the Faulting state to move to the Stopped state, the external agent must:
• Program the DBGINST0 register with the encoding for the DMAKILL instruction.
• Write to the DBGCMD register.
Note:
If the aborted thread is secure, you must use the secure slave interface to update these registers.
After a thread in the Faulting state executes DMAKILL, it moves to the Stopped state.
Security Usage
When the DMAC exits from reset, the status of the configuration signals configures the security for:
• DMA manager thread The DNS bit in the DSR register returns the security state of the DMA manager
thread.
• Events and interrupts The INS bit in the CR3 register returns the security state of the event-interrupt
resources.
• Peripheral request interfaces The PNS bit in the CR4 register returns the security state of these interfaces.
Additionally, each DMA channel thread contains a dynamic non-secure bit, CNS, that is valid when the
channel is not in the Stopped state.
Altera Corporation
cv_54016
2013.12.30
DMA Controller
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