Dma Controller Programming Model; Instruction Syntax Conventions - Altera Cyclone V Device Handbook

16-26
Clocks and Resets
• MFIFO Buffer Usage Overview
Clocks and Resets
Clock
The DMA controller operates on the l4_main_clk input.
Related Information
Clock Manager
Resets
The DMA controller has nine reset signals. The reset manager drives dma_rst_n signal to the DMA
controller on a cold or warm reset. The peripheral request interface logic for STM and QSPI are reset when
the corresponding peripheral is reset. The following table lists the DMA controller reset inputs.
Table 16-2: Reset inputs to the DMA controller
dma_rst_n
dma_periph_if_rst_n[7:0]
Related Information
Reset Manager

DMA Controller Programming Model

Instruction Syntax Conventions

The following conventions are used in assembler syntax prototype lines and their subfields:
• < >
Any item bracketed by < and > is mandatory. A description of the item and of how it is encoded in the
instruction is supplied by subsequent text.
• [ ]
Any item bracketed by [ and ] is optional. A description of the item and of how its presence or absence is
encoded in the instruction is supplied by subsequent text.
• Spaces
To separate items, single spaces are used for clarity. When a space is obligatory in the assembler syntax, two
or more consecutive spaces are used.
Altera Corporation
on page 16-44
on page 2-1
Reset Signal
on page 3-1
Description
Resets DMA controller
Resets the eight FPGA peripheral request interfaces
cv_54016
2013.12.30
DMA Controller
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