Instructions - Altera Cyclone V Device Handbook

16-28

Instructions

Mnemonic
DMAWFP Wait For Peripheral
DMAWMB Write Memory
Barrier
Instructions
DMAADDH
Add Halfword adds an immediate 16-bit value to the SARn register or DARn register, for the DMA channel
thread. This enables the DMAC to support two-dimensional DMA operations.
Note: The immediate unsigned 16-bit value is zero-extended before the DMAC adds it to the address, using
32-bit addition. The DMAC discards the carry bit so that addresses wrap from 0xFFFFFFFF to
0x00000000.
Figure 16-5: DMAADDH Instruction Encoding
Assembler syntax
DMAADDH <address_register>, <16-bit bit immediate>
where:
<address_register> Selects the address register to use. It must be either:
• SAR SARn register and sets ra to 0
• DAR DARn register and sets ra to 1
<16-bit immediate> The immediate value to be added to the <address_register>.
Operation
You can only use this instruction in a DMA channel thread.
DMAADNH
Add Negative Halfword adds an immediate negative 16-bit value to the SARn register or DARn register, for
the DMA channel thread. This enables the DMAC to support two-dimensional DMA operations, or reading
or writing an area of memory in a different order to naturally incrementing addresses.
Note: The immediate unsigned 16-bit value is one-extended to 32 bits, to create a value that is the two's
complement representation of a negative number between -65536 and -1, before the DMAC adds it
to the address using 32-bit addition. The DMAC discards the carry bit so that addresses wrap from
0xFFFFFFFF to 0x00000000. The net effect is to subtract between 65536 and 1 from the current value
in the source or destination address register.
Altera Corporation
Instruction DMA Manager Usage
No
No
23 16
imm[15:8]
DMA Channel Usage
Yes
Yes
15 8 7 6 5 4
imm[7:0] 0 1 0
ra10110101rara 1
Description
DMAWFP on page 16-41
DMAWMB on page 16-42
3 2 1 0
1 0 1 ra 0
DMA Controller
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2013.12.30