Reset Controller - Altera Cyclone V Device Handbook

3-4

Reset Controller

Source
f2h_warm_rst_req_n
f2h_dbg_rst_req_n
h2f_cold_rst_n
h2f_rst_n
h2f_dbg_rst_n
load_csr
nPOR
nRST
Reset Controller
The reset controller performs the following functions:
• Accepts reset requests from the FPGA CB, FPGA fabric, modules in the HPS, and reset pins
• Generates an individual reset signal for each module instance for all modules in the HPS
• Provides reset handshaking signals to support system reset behavior
The reset controller generates module reset signals from external reset requests and internal reset requests.
External reset requests originate from sources external to the reset manager. Internal reset requests originate
from control registers in the reset manager.
Altera Corporation
Warm reset request from FPGA fabric (active low)
Debug reset request from FPGA fabric (active low)
Cold-only reset to FPGA fabric (active low)
Cold or warm reset to FPGA fabric (active low)
Debug reset (dbg_rst_n) to FPGA fabric (active low)
Cold-only reset from FPGA control block (CB) and scan manager
Power-on reset pin (active low)
Warm reset pin (active low)
Description
Send Feedback
cv_54003
2013.12.30
Reset Manager