Altera Cyclone V Device Handbook page 876

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2013.12.30
2. When Bit 13 (ST) of Register 6 (Operation Mode Register) is set, the DMA enters the Run state.
3. While in the Run state, the DMA polls the transmit descriptor list for frames requiring transmission.
After polling starts, it continues in either sequential descriptor ring order or chained order. If the DMA
detects a descriptor flagged as owned by the Host (TDES0[31] = 0), or if an error condition occurs,
transmission is suspended and both the Bit 2 (Transmit Buffer Unavailable) and Bit 16 (Normal Interrupt
Summary) of the Register 5 (Status Register) are set. The transmit Engine proceeds to
4. If the acquired descriptor is flagged as owned by DMA (TDES0[31] = 1), the DMA decodes the transmit
Data Buffer address from the acquired descriptor.
5. The DMA fetches the transmit data from the Host memory and transfers the data to the MTL for
transmission.
6. If an Ethernet frame is stored over data buffers in multiple descriptors, the DMA closes the intermediate
descriptor and fetches the next descriptor. Repeat
frame data is transferred to the MTL.
7. When frame transmission is complete, if IEEE 1588 timestamping was enabled for the frame (as indicated
in the transmit status) the timestamp value obtained from MTL is written to the transmit descriptor
(TDES2 and TDES3) that contains the end-of-frame buffer. The status information is then written to
this transmit descriptor (TDES0). Because the Own bit is cleared during this step, the Host now owns
this descriptor. If timestamping was not enabled for this frame, the DMA does not alter the contents of
TDES2 and TDES3.
8. Bit 0 (Transmit Interrupt) of Register 5 (Status Register) is set after completing transmission of a frame
that has Interrupt on Completion (TDES1[31]) set in its Last descriptor. The DMA engine then returns
to step
9. In the Suspend state, the DMA tries to re-acquire the descriptor (and thereby return to
receives a Transmit Poll demand and the Underflow Interrupt Status bit is cleared.
Ethernet Media Access Controller
Send Feedback
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†
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3.
TX DMA Operation: Default (Non-OSF) Mode
step 3, step
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step
4, and step 5 until the end-of-Ethernet-
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17-27
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9.
step 3) when it
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