Phy Management Interface; Ieee 1588 - Altera Cyclone V Device Handbook

17-8

PHY Management Interface

Signal Name
gmii_mdc_o
PHY Management Interface
The HPS can provide support for either MDIO or I
MDIO Interface
The MDIO interface signals are synchronous to l4_mp_clk in all supported modes.
Table 17-3: PHY MDIO Management Interface
Signal
gmii_mdi_i
gmii_mdo_o
gmii_mdo_o_e
gmii_mdc_o
2
I C External PHY Management Interface
Some PHY devices use the I
(SFP) optical or pluggable modules are often among those with this interface.
The HPS can use two of the four general purpose I

IEEE 1588

The EMAC supports IEEE 1588 operation in all modes with a resolution of one µs. It can be used by the
® ™
ARM Cortex
counters internal to the two MACs.
Altera Corporation
In/Out
Out
In/Out
In
Out
Out
Out
2
C instead of MDIO for their control interface. Small form factor pluggable
-A9 microprocessor unit (MPU) subsystem to maintain synchronization between the time
Width
1 Management Data Clock. The maximum
frequency of this clock is 2.5 MHz. This clock
is generated from the application clock through
a clock divider.
2
C PHY management interfaces.
Width
1 Management Data In. The PHY generates this
signal to transfer register data during a read
operation. This signal is driven synchronously
with the gmii_mdc_o clock.
1 Management Data Out. The EMAC uses this
signal to transfer control and data information to
the PHY.
1 Management Data Output Enable. This enable
signal drives the gmii_mdo_o signal from an
external three-state I/O buffer. This signal is
asserted whenever valid data is driven on the
gmii_mdo_o signal. The active state of this signal
is high.
1 Management Data Clock. The EMAC provides
timing reference for the gmii_mdi_i and
gmii_mdo_o signals on MII through this
aperiodic clock. The maximum frequency of this
clock is 2.5 MHz. This clock is generated from the
application clock through a clock divider.
2
C peripherals for controlling the PHY devices.
Description
Description
Ethernet Media Access Controller
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2013.12.30