Altera Cyclone V Device Handbook page 72

CV-52004
2014.01.10
Figure 4-13:
clkena
This figure shows the implementation of the clock enable and disable circuit of the clock control block.
The
clkena
allows you to gate off the clock even when you are not using a PLL. You can also use the
control the dedicated external clocks from the PLLs.
Figure 4-14: Example of
This figure shows a waveform example for a clock output enable. The
falling edge of the clock output.
Use the clkena signals to
enable or disable the GCLK
and RCLK networks or the
FPLL_<#>_CLKOUT pins.
(ena Port Registered as
Falling Edge of Input Clock)
with R2 Not Bypassed
(ena Port Registered as Double
Register with Input Clock)
Cyclone V devices have an additional metastability register that aids in asynchronous enable and disable of
the GCLK and RCLK networks. You can optionally bypass this register in the Quartus II software.
The PLL can remain locked, independent of the
affected. This feature is useful for applications that require a low-power or sleep mode. The
can also disable clock outputs if the system is not tolerant of frequency overshoot during resynchronization.
Clock Networks and PLLs in Cyclone V Devices
Send Feedback
Implementation with Clock Enable and Disable Circuit
clkena
D
Clock Select
Multiplexer Output
R1
signals are supported at the clock network level instead of at the PLL output counter level. This
Signals
clkena
Clock Select
Multiplexer Output
clkena
AND Gate Output
with R2 Bypassed
AND Gate Output
Q D Q
R2
signals, because the loop-related counters are not
clkena
Clock Enable Signals
The R1 and R2 bypass paths
are not available for the PLL
external clock outputs.
GCLK/
RCLK/
FPLL_<#>_CLKOUT
The select line is statically
controlled by a bit setting in
the .sof or .pof.
clkena
signal is synchronous to the
clkena
clkena
Altera Corporation
4-15
signals to
signal