Altera Cyclone V Device Handbook page 83

4-26
Source Synchronous Mode
Source Synchronous Mode
If the data and clock arrive at the same time on the input pins, the same phase relationship is maintained at
the clock and data ports of any IOE input register. Data and clock signals at the IOE experience similar buffer
delays as long as you use the same I/O standard.
Altera recommends source synchronous mode for source synchronous data transfers.
Figure 4-25: Example of Phase Relationship Between Clock and Data in Source Synchronous Mode
The source synchronous mode compensates for the delay of the clock network used and any difference in
the delay between the following two paths:
Data pin to the IOE register input
Clock input pin to the PLL phase frequency detector (PFD) input
The Cyclone V PLL can compensate multiple pad-to-input-register paths, such as a data bus when it is set
to use source synchronous compensation mode.
LVDS Compensation Mode
The purpose of LVDS compensation mode is to maintain the same data and clock timing relationship seen
at the pins of the internal serializer/deserializer (SERDES) capture register, except that the clock is inverted
(180° phase shift). Thus, LVDS compensation mode ideally compensates for the delay of the LVDS clock
network, including the difference in delay between the following two paths:
Data pin-to-SERDES capture register
Clock input pin-to-SERDES capture register
The output counter must provide the 180° phase shift.
Altera Corporation
Data Pin
PLL Reference Clock
at the Input Pin
Data at the Register
Clock at the Register
Clock Networks and PLLs in Cyclone V Devices
CV-52004
2014.01.10
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