Altera Cyclone V Device Handbook page 358

2-20
FPGA Fabric Transceiver Interface Clocking
Table 2-9: FPGA Fabric Transceiver Interface Clocks
Clock Name
tx_pll_refclk, rx_cdr_
refclk
tx_clkout, tx_pma_clkout
rx_clkout, rx_pma_clkout
tx_coreclkin
rx_coreclkin
fixed_clk
mgmt_clk
Note: For more information about the GCLK, RCLK, and PCLK resources available in each device, refer
to the Clock Networks and PLLs in Cyclone V Devices chapter.
(9)
The mgmt_clk is a free-running clock that is not derived from the transceiver blocks.
Altera Corporation
Clock Description
Input reference
clock used for
clocking logic in
the FPGA fabric
Clock
forwarded by
the transceiver
for clocking
the transceiver
datapath
interface
Clock
forwarded by
the receiver
for clocking
the receiver
datapath
interface
User-selected
clock for clocking
the transmitter
datapath interface
User-selected
clock for
clocking the
receiver
datapath
interface
PCIe receiver
detect clock
(9)
Avalon-MM
interface
management
clock
Interface Direction
Transceiver-to-FPGA
fabric
FPGA fabric-to-
transceiver
Transceiver Clocking in Cyclone V Devices
FPGA Fabric Clock Resource
Utilization
GCLK, RCLK, PCLK
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CV-53002
2013.05.06