Altera Cyclone V Device Handbook page 782

14-4
NAND Flash Controller
NAND Flash Controller
The bootstrap control register (nand_bootstrap) modifies the default behavior of the NAND flash
controller after reset. The NAND flash controller samples the register bits when it comes out of reset.
The following bootstrap register bits control configuration of the NAND flash controller:
• Bootstrap inhibit initialization bit (noinit) inhibits the NAND flash controller from initializing when
coming out of reset, and allows software to program all registers pertaining to device parameters such as
page size and width.
• Bootstrap 512 byte device bit (page512) informs the NAND flash controller that a NAND flash device
of 512 byte page size is connected to the system.
• Bootstrap inhibit load block 0 page 0 bit (noloadb0p0) inhibits the NAND flash controller from
loading page 0 of block 0 of the NAND flash device as part of the initialization procedure.
• Bootstrap two row address cycles bit (tworowaddr) informs the NAND flash controller that only
two ROW address cycles are required instead of the default three row address cycles.
Registers in the system manager control the L3 master ARCACHE and AWCACHE signals. Set the NAND
arcache (arcache) and NAND awcache (awcache) bits of the NAND L3 master AxCACHE register
(l3master) to control these selections. These bits define the cache attributes for the master transactions
of the DMA engine in the NAND controller.
Note: Register bits should be accessed only when the master interface is guaranteed to be in an inactive
state.
Related Information
NAND Flash Controller
EMAC
The system manager allows software to select either emac_ptp_clk from the Clock Manager or
f2s_ptp_ref_clk from the FPGA Fabric as the source of the IEEE 1588 reference clock for each EMAC.
Registers in the system manager control the L3 master ARCACHE and AWCACHEsignals. Set the EMAC
arcache, awcache, and arprot, awprot bits to control these selections. These bits define the cache
attributes for the master transactions of the DMA engine in the EMAC controllers.
The app_clk_sel bit determines the source of the clocks for the application clock. The ptp_ref_sel
bit selects if the Timestamp reference is internally or externally generated. Note that EMAC0 must be set to
Internal Timestamp. The phy_intf_sel bit determines if Out of Reset, GMII (or MII), RGMII or RMII
would be used as the PHY interface.
Note: Register bits should be accessed only when the master interface is guaranteed to be in an inactive
state.
Related Information
• Clock Manager
• Ethernet Media Access Controller
Altera Corporation
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System Manager
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