L4 Slave Interface; Clocks - Altera Cyclone V Device Handbook

cv_54025
2013.12.30
Figure 25-3: CAN Core in Loopback Mode
Combined Mode
The CAN controller is set in combined loopback and silent mode by programming the silent mode (Silent)
and loopback mode (LBack) bits in the test register (CTR) to 1. Combined mode can be used for testing
the CAN hardware without affecting other devices connected to the CAN bus. In this mode, the CAN_RXD
pin is disconnected from the CAN core and the CAN_TXD pin is held high.
Figure 25-4: CAN Core in Combined Mode

L4 Slave Interface

The host processor accesses data, control, and status information of the CAN controller through the L4 slave
interface. The slave interface supports 32-bit accesses only.
Note: This interface does not support error responses.

Clocks

The CAN controller operates on the l4_sp_clk and can_clk clock inputs. The l4_sp_clk clock is
used by the L4 slave interface and the can_clk is used to operate the CAN core.
The can_clk clock must be programmed to be at least eight times the CAN bus interface speed. For
example, for a CAN bus interface operating at a 1 Mbps baud rate, the can_clk clock must be set to at
least 8 MHz. The l4_sp_clk clock can operate at a clock frequency that is equal to or greater than the
can_clk frequency.
Related Information
Clock Manager
For more information about the l4_sp_clk and can_clk clocks, refer to the Clock Manager chapter in
the Cyclone V Device Handbook, Volume 3.
CAN Controller Introduction
Send Feedback
CAN_RXD
CAN_TXD
CAN_RXD
CAN_TXD
on page 2-1
CAN Controller
RX
TX
CAN Core
CAN Controller
RX
V
TX
cc
CAN Core
25-9
Combined Mode
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