Altera Cyclone V Device Handbook page 402

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XAUI Supported Features

Figure 4-20: Implementation of the XGMII Specification in Cyclone V Devices Configuration

8B/10B Encoding/Decoding

Each of the four lanes in a XAUI configuration support an independent 8B/10B encoder/decoder as specified

in Clause 48 of the IEEE802.3-2008 specification. 8B/10B encoding limits the maximum number of

consecutive 1s and 0s in the serial data stream to five, thereby ensuring DC balance as well as enough

transitions for the receiver CDR to maintain a lock to the incoming data.

The XAUI PHY IP core provides status signals to indicate running disparity as well as the 8B/10B code group

Transmitter and Receiver State Machines

In a XAUI configuration, the Cyclone V soft PCS implements the transmitter and receiver state diagrams

shown in Figure 48-6 and Figure 48-9 of the IEEE802.3-2008 specification.

In addition to encoding the XGMII data to PCS code groups, in conformance with the 10GBASE-X PCS,

the transmitter state diagram performs functions such as converting Idle ||I|| ordered sets into Sync ||K||,

Align ||A||, and Skip ||R|| ordered sets.

In addition to decoding the PCS code groups to XGMII data, in conformance with the 10GBASE-X PCS,

the receiver state diagram performs functions such as converting Sync ||K||, Align ||A||, and Skip ||R|| ordered

sets to Idle ||I|| ordered sets.

Altera Corporation

XGMII Transfer (DDR)

Interface Clock (156.25 MHz)

Cyclone V Soft PCS Interface (SDR)

Interface Clock (156.25 MHz)

Transceiver Protocol Configurations in Cyclone V Devices

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