Configuration Sequence - Altera Cyclone V Device Handbook

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Table 7-2: MSEL Pin Settings for Each Configuration Scheme of Cyclone V Devices

Configuration Scheme

AS (x1 and x4)

configuration

You must also select the configuration scheme in the Configuration page of the Device and Pin

Options dialog box in the Quartus II software. Based on your selection, the option bit in the

programming file is set accordingly.

Related Information

FPGA Manager

Provides more information about the MSEL pin settings for configuration with hard processor system

(HPS) in system on a chip (SoC) FPGA devices.

Cyclone V Device Family Pin Connection Guidelines

Provides more information about JTAG pins voltage-level connection.

Configuration Sequence

Describes the configuration sequence and each configuration stage.

For configuration with HPS in SoC FPGA devices, refer to the FPGA Manager for the related MSEL pin settings.

Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices

Send Feedback

Design Security

Configuration Sequence

Power-On Reset

1.8/2.5/3.0/3.3

1.8/2.5/3.0/3.3

1.8/2.5/3.0/3.3

1.8/2.5/3.0/3.3

1.8/2.5/3.0/3.3

1.8/2.5/3.0/3.3

1.8/2.5/3.0/3.3

Valid MSEL[4..0]

Use any valid

settings above

Altera Corporation

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