Altera Cyclone V Device Handbook page 248

CV-52007
2014.01.10
Control Register
Table 7-7: Control Register Bits
Bit
0
1..24
25
26..37
Status Register
Table 7-8: Status Register Bits
Bit
0
1
2
3
4
(18)
This is the default value after the device exits POR and during reconfiguration back to the factory configuration
image.
(19)
After the device exits POR and power-up, the status register content is 5'b00000.
Configuration, Design Security, and Remote System Upgrades in Cyclone V Devices
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Name
AnF
PGM[0..23]
Wd_en
Wd_timer[11..0]
Name
Value
1'b0
CRC
1'b0
nSTATUS
1'b0
Core_nCONFIG
1'b0
nCONFIG
1'b0
Wd
Reset
(18)
Value
1'b0 Application not Factory bit. Indicates the
configuration image type currently loaded in
the device; 0 for factory image and 1 for
application image. When this bit is 1, the access
to the control register is limited to read only
and the watchdog timer is enabled.
Factory configuration design must set this bit
to 1 before triggering reconfiguration using an
application configuration image.
24'h000000 Upper 24 bits of AS configuration start address
(
StAdd[31..8]
1'b0 User watchdog timer enable bit. Set this bit to
1 to enable the watchdog timer.
12' b 000000000000 User watchdog time-out value.
Reset
(19)
When set to 1, indicates CRC error during application
configuration.
When set to 1, indicates that
external device due to error.
When set to 1, indicates that reconfiguration has been
triggered by the logic array of the device.
When set to 1, indicates that
When set to 1, indicates that the user watchdog
time-out.
Control Register
Description
), the 8 LSB are zero.
Description
is asserted by an
nSTATUS
is asserted.
nCONFIG
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