Enabling The Timer; Disabling The Timer; Loading The Timer Countdown Value; Servicing Interrupts - Altera Cyclone V Device Handbook

23-4

Enabling the Timer

3. Enable the timer by writing a 1 to the timer1_enable bit of the timer1controlreg register. †
Enabling the Timer
When a timer transitions to the enabled state, the current value of timer1loadcount register is loaded
into the timer counter. †
1. To enable the timer, write a 1 to the timer1_enable bit of the timer1controlreg register.

Disabling the Timer

When the timer enable bit is cleared to 0, the timer counter and any associated registers in the timer clock
domain, are asynchronously reset. †
1. To disable the timer, write a 0 to the timer1_enable bit. †

Loading the Timer Countdown Value

When a timer counter is enabled after being reset or disabled, the count value is loaded from the
timer1loadcount register; this occurs in both free-running and user-defined count modes. †
When a timer counts down to 0, it loads one of two values, depending on the timer operating mode: †
• User-defined count mode timer loads the current value of the timer1loadcount register. Use this
mode if you want a fixed, timed interrupt. Designate this mode by writing a 1 to the timer1_mode bit
of the timer1controlreg register. †
• Free-running mode timer loads the maximum value (0xFFFFFFFF). The timer max count value allows
for a maximum amount of time to reprogram or disable the timer before another interrupt occurs. Use
this mode if you want a single timed interrupt. Enable this mode by writing a 0 to the timer1_mode
bit of the timer1controlreg register. †

Servicing Interrupts

Clearing the Interrupt
An active timer interrupt can be cleared in two ways.
1. If you clear the interrupt at the same time as the timer reaches 0, the interrupt remains asserted. This
action happens because setting the timer interrupt takes precedence over clearing the interrupt. †
2. To clear an active timer interrupt, read the timer1eoi register or disable the timer. When the timer
is enabled, its interrupt remains asserted until it is cleared by reading the timer1eoi register. †
Checking the Interrupt Status
You can query the interrupt status of the timer without clearing its interrupt.
1. To check the interrupt status, read the timer1intstat register. †
Masking the Interrupt
The timer interrupt can be masked using the timer1controlreg register.
1. To mask an interrupt, write a 1 to the timer1_interrupt_mask bit of the timer1controlreg
register. †
Altera Corporation
cv_54023
2013.12.30
Timer Introduction
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